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AD9272-80KITZ1 데이터시트(PDF) 9 Page - Analog Devices

부품명 AD9272-80KITZ1
상세설명  Octal LNA/VGA/AAF/ADC and Crosspoint Switch
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AD9272
Rev. C | Page 9 of 44
SWITCHING SPECIFICATIONS
AVDD1 = 1.8 V, AVDD2 = 3.0 V, DRVDD = 1.8 V, 1.0 V internal ADC reference, fIN = 5 MHz, full temperature, unless otherwise noted.
Table 3.
Parameter1
Temp
Min
Typ
Max
Unit
CLOCK2
Clock Rate
Full
10
80
MSPS
Clock Pulse Width High (tEH)
Full
6.25
ns
Clock Pulse Width Low (tEL)
Full
6.25
ns
OUTPUT PARAMETERS2, 3
Propagation Delay (tPD)
Full
(tSAMPLE/2) + 1.5
(tSAMPLE/2) + 2.3
(tSAMPLE/2) + 3.1
ns
Rise Time (tR) (20% to 80%)
Full
300
ps
Fall Time (tF) (20% to 80%)
Full
300
ps
FCO± Propagation Delay (tFCO)
Full
(tSAMPLE/2) + 1.5
(tSAMPLE/2) + 2.3
(tSAMPLE/2) + 3.1
ns
DCO± Propagation Delay (tCPD)4
Full
tFCO + (tSAMPLE/24)
ns
DCO± to Data Delay (tDATA)4
Full
(tSAMPLE/24) − 300
(tSAMPLE/24)
(tSAMPLE/24) + 300
ps
DCO± to FCO± Delay (tFRAME)4
Full
(tSAMPLE/24) − 300
(tSAMPLE/24)
(tSAMPLE/24) + 300
ps
Data-to-Data Skew
(tDATA-MAX − tDATA-MIN)
Full
±100
±350
ps
Wake-Up Time (Standby), GAIN+ = 0.8 V
25°C
2
μs
Wake-Up Time (Power-Down)
25°C
1
ms
Pipeline Latency
Full
8
Clock cycles
APERTURE
Aperture Uncertainty (Jitter)
25°C
<1
ps rms
1 See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions and information about how these tests were
completed.
2 Can be adjusted via the SPI.
3 Measurements were made using a part soldered to FR-4 material.
4 tSAMPLE/24 is based on the number of bits divided by 2 because the delays are based on half duty cycles.


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