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LAN8710A-EZC 데이터시트(PDF) 30 Page - SMSC Corporation |
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LAN8710A-EZC 데이터시트(HTML) 30 Page - SMSC Corporation |
30 / 82 page Small Footprint MII/RMII 10/100 Ethernet Transceiver with HP Auto-MDIX and flexPWR® Technology Datasheet Revision 1.4 (08-23-12) 30 SMSC LAN8710A/LAN8710Ai DATASHEET 3.4 MAC Interface The MII/RMII block is responsible for communication with the MAC controller. Special sets of hand- shake signals are used to indicate that valid received/transmitted data is present on the 4 bit receive/transmit bus. The device must be configured in MII or RMII mode. This is done by specific pin strapping configurations. Refer to Section 3.4.3, "MII vs. RMII Configuration," on page 31 for information on pin strapping and how the pins are mapped differently. 3.4.1 MII The MII includes 16 interface signals: transmit data - TXD[3:0] transmit strobe - TXEN transmit clock - TXCLK transmit error - TXER/TXD4 receive data - RXD[3:0] receive strobe - RXDV receive clock - RXCLK receive error - RXER/RXD4/PHYAD0 collision indication - COL carrier sense - CRS In MII mode, on the transmit path, the transceiver drives the transmit clock, TXCLK, to the controller. The controller synchronizes the transmit data to the rising edge of TXCLK. The controller drives TXEN high to indicate valid transmit data. The controller drives TXER high when a transmit error is detected. On the receive path, the transceiver drives both the receive data, RXD[3:0], and the RXCLK signal. The controller clocks in the receive data on the rising edge of RXCLK when the transceiver drives RXDV high. The transceiver drives RXER high when a receive error is detected. 3.4.2 RMII The device supports the low pin count Reduced Media Independent Interface (RMII) intended for use between Ethernet transceivers and switch ASICs. Under IEEE 802.3, an MII comprised of 16 pins for data and control is defined. In devices incorporating many MACs or transceiver interfaces such as switches, the number of pins can add significant cost as the port counts increase. RMII reduces this pin count while retaining a management interface (MDIO/MDC) that is identical to MII. The RMII interface has the following characteristics: It is capable of supporting 10Mbps and 100Mbps data rates A single clock reference is used for both transmit and receive It provides independent 2-bit (di-bit) wide transmit and receive data paths It uses LVCMOS signal levels, compatible with common digital CMOS ASIC processes The RMII includes the following interface signals (1 optional): transmit data - TXD[1:0] transmit strobe - TXEN receive data - RXD[1:0] receive error - RXER (Optional) |
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