전자부품 데이터시트 검색엔진 |
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LAN8710A-EZC 데이터시트(PDF) 81 Page - SMSC Corporation |
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LAN8710A-EZC 데이터시트(HTML) 81 Page - SMSC Corporation |
81 / 82 page Small Footprint MII/RMII 10/100 Ethernet Transceiver with HP Auto-MDIX and flexPWR® Technology Datasheet SMSC LAN8710A/LAN8710Ai 81 Revision 1.4 (08-23-12) DATASHEET Chapter 7 Datasheet Revision History Table 7.1 Customer Revision History REVISION LEVEL & DATE SECTION/FIGURE/ENTRY CORRECTION Rev. 1.4 (08-23-12) Section 4.2.2, "Basic Status Register," on page 53 Updated definitions of bits 10:8. Section 4.2.11, "Special Control/Status Indications Register," on page 62 Updated bit 11 definition. Section 4.2.14, "PHY Special Control/Status Register," on page 65 Updated bit 6 definition. Rev. 1.3 (03-12-12) Company disclaimer on page 2 Removed company address and phone numbers. Cover Ordering information modified. Rev. 1.3 (04-20-11) Cover Added copper bond wire ordering codes to LAN8710 ordering codes Table 2.7, “Power Pins,” on page 16 Updated VDDCR pin note to include requirement of 1uF and 470pF decoupling capacitors in parallel to ground on the VDDCR pin. Figure 3.13 Power Supply Diagram (1.2V Supplied by Internal Regulator) on page 46 and Figure 3.13 Power Supply Diagram (1.2V Supplied by Internal Regulator) on page 46 Updated diagrams to include 1uF and 470pF decoupling capacitors on the VDDCR pin. Table 4.2.9, “Special Modes Register,” on page 60 Updated MIIMODE bit description and added note: “When writing to this register the default value of this bit must always be written back.” Section 3.7.3, "RMIISEL: MII/RMII Mode Configuration," on page 37 Updated second paragraph to: “When the nRST pin is deasserted, the MIIMODE bit of the Special Modes Register is loaded according to the RMIISEL configuration strap. The mode is reflected in the MIIMODE bit of the Special Modes Register.” Section 3.8.9.2, "Far Loopback," on page 43 Updated section to defeature information about register control of the MII/RMII mode. Rev. 1.2 (11-10-10) Section 5.5.5, "RMII Interface Timing," on page 75 Updated diagrams and tables to include RXER. Figure 6.1 32-QFN Package on page 78 & Figure 6.2 Recommended PCB Land Pattern on page 79 Updated package drawings. Section 5.5.5, "RMII Interface Timing," on page 75 Corrected signal names on RMII timing diagrams and tables. |
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