© 2002 Fairchild Semiconductor Corporation

DS500654

www.fairchildsemi.com

January 2002

Revised September 2002

FIN1101

LVDS Single Port High Speed Repeater

General Description

This single port repeater is designed for high speed inter-

connects

utilizing

Low

Voltage

Differential

Signaling

(LVDS) technology. It accepts and outputs LVDS levels

with a typical differential output swing of 330 mV which pro-

vides low EMI at ultra low power dissipation even at high

frequencies. It can directly accept multiple differential I/O

including: LVPECL, HSTL, and SSTL-2 for translating

directly to LVDS.

Features

s Up to 1.6 Gb/s full differential path

s 3.5 ps max random jitter and 135 ps max deterministic

jitter

s 3.3V power supply operation

s Wide rail-to-rail common mode range

s Ultra low power consumption

s LVDS receiver inputs accept LVPECL, HSTL, and

SSTL-2 directly

s Power off protection

s 7 kV HBM ESD protection (all pins)

s Meets or exceed the TA/EIA-644-A LVDS standard

s Packaged in 8-pin SOIC and US8

s Open circuit fail safe protection

Ordering Code:

Connection Diagrams

SOIC Package

US8 Package

Functional Diagram

Pin Descriptions

Function Table

H

= HIGH Logic Level

L

= LOW Logic Level

X

= Don’t Care

Z

= High Impedance

Order Number

Package Number

Package Description

FIN1101M

M08A

8-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow

[TUBE]

FIN1101MX

M08A

8-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow

[TAPE and REEL]

FIN1101K8X

MAB08A

8-Lead US8, JEDEC MO-187, Variation CA 3.1mm Wide

[TAPE and REEL]

Pin Name

Description

Non-Inverting LVDS Inputs

Inverting LVDS Inputs

Non-Inverting Driver Outputs

Inverting Driver Outputs

EN

Driver Enable Pin

Power Supply

GND

Ground

Inputs

Outputs

EN

HH

L

H

L

HL

H

L

H

H

Fail Safe Case

H

L

LX

X

Z

Z