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ADV7179WBCPZ2 데이터시트(PDF) 5 Page - Analog Devices |
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ADV7179WBCPZ2 데이터시트(HTML) 5 Page - Analog Devices |
5 / 52 page ADV7174/ADV7179 Rev. B | Page 5 of 52 2.8 V TIMING SPECIFICATIONS VAA = 2.8 V, VREF = 1.235 V, RSET = 150 Ω. All specifications TMIN to TMAX1, unless otherwise noted. Table 2. Parameter Conditions1 Min Typ Max Unit MPU PORT2, 3 SCLOCK Frequency 0 400 kHz SCLOCK High Pulse Width, t1 0.6 μs SCLOCK Low Pulse Width, t2 1.3 μs Hold Time (Start Condition), t3 After this period the first clock is generated 0.6 μs Setup Time (Start Condition), t4 Relevant for repeated start condition 0.6 μs Data Setup Time, t5 100 ns SDATA, SCLOCK Rise Time, t6 300 ns SDATA, SCLOCK Fall Time, t7 300 ns Setup Time (Stop Condition), t8 0.6 μs ANALOG OUTPUTS3, 4 Analog Output Delay 7 ns DAC Analog Output Skew 0 ns CLOCK CONTROL AND PIXEL PORT4, 5 fCLOCK 27 MHz Clock High Time, t9 8 ns Clock Low Time, t10 8 ns Data Setup Time, t11 3.5 ns Data Hold Time, t12 4 ns Control Setup Time, t11 4 ns Control Hold Time, t12 3 ns Digital Output Access Time, t13 12 ns Digital Output Hold Time, t14 8 ns Pipeline Delay, tPD5 48 Clock Cycles TELETEXT3, 4, 6 Digital Output Access Time, t16 23 ns Data Setup Time, t17 2 ns Data Hold Time, t18 6 ns RESET CONTROL ,3 4 RESET Low Time 6 ns 1 Temperature range TMIN to TMAX: –20°C to +85°C. 2 TTL input values are 0 V to 2.8 V, with input rise/fall times −3 ns, measured between the 10% and 90% points. Timing reference points at 50% for inputs and outputs. Analog output load –10 pF. 3 Guaranteed by characterization. 4 Output delay measured from the 50% point of the rising edge of CLOCK to the 50% point of full-scale transition. 5 See Figure 60. 6 Teletext Port consists of the following: Teletext Output: TTXREQ Teletext Input: TTX |
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