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FM27C010NE150 데이터시트(PDF) 4 Page - Fairchild Semiconductor |
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FM27C010NE150 데이터시트(HTML) 4 Page - Fairchild Semiconductor |
4 / 10 page 4 www.fairchildsemi.com www.fairchildsemi.com FM27C010 AC Test Conditions Output Load 1 TTL Gate and C L = 100 pF (Note 8) Input Rise and Fall Times ≤5 ns Input Pulse Levels 0.45V to 2.4V Timing Measurement Reference Level Inputs 0.8V and 2V Outputs 0.8V and 2V AC Waveforms (Note 6), (Note 7), and (Note 9) Note 1: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Note 2: This parameter is only sampled and is not 100% tested. Note 3: OE may be delayed up to t ACC - tOE after the falling edge of CE without impacting tACC. Note 4: The tDF and tCF compare level is determined as follows: High to TRI-STATE®, the measured VOH1 (DC) - 0.10V; Low to TRI-STATE, the measured VOL1 (DC) + 0.10V. Note 5: TRI-STATE may be attained using OE or CE. Note 6: The power switching characteristics of EPROMs require careful device decoupling. It is recommended that at least a 0.1 µF ceramic capacitor be used on every device between VCC and GND. Note 7: The outputs must be restricted to V CC + 1.0V to avoid latch-up and device damage. Note 8: 1 TTL Gate: I OL = 1.6 mA, IOH = -400 µA. C L: 100 pF includes fixture capacitance. Note 9: V PP may be connected to VCC except during programming. Note 10: Inputs and outputs can undershoot to -2.0V for 20 ns Max. Programming Characteristics (Note 11), (Note 12), (Note 13), and (Note 14) Symbol Parameter Conditions Min Typ Max Units tAS Address Setup Time 1 µs t OES OE Setup Time 1 µs tCES CE Setup Time OE = VIH 1 µs t DS Data Setup Time 1 µs tVPS VPP Setup Time 1 µs t VCS V CC Setup Time 1 µs tAH Address Hold Time 0 µs t DH Data Hold Time 1 µs tDF Output Enable to Output Float Delay CE = VIL 060 ns t PW Program Pulse Width 45 50 105 µs Address Valid Valid Output Hi-Z 2V 0.8V 2V 0.8V 2V 0.8V ADDRESS OUTPUT CE OE tCE 2V 0.8V (Note 3) (Note 3) tDF (Note 4, 5) (Note 4, 5) tOH Hi-Z tOE tACC tCF DS800032-4 |
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