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FM93C56V 데이터시트(PDF) 10 Page - Fairchild Semiconductor |
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FM93C56V 데이터시트(HTML) 10 Page - Fairchild Semiconductor |
10 / 13 page 10 www.fairchildsemi.com FM93C56 Rev. C.1 Timing Diagrams (Continued) CS SK DI DO High - Z High - Z CLEARING READY STATUS Star t Bit Note: This Star t bit can also be par t of a next instr uction. Hence the cycle can be continued (instead of getting ter minated, as shown) as if a new instr uction is being issued. Busy Ready Address Bits(8) CS SK DI DO High - Z tCS ERASE CYCLE (ERASE) Star t Bit 93C56: Address bits patter n -> 0-A6-A5-A4-A3-A2-A1-A0; (A6-A0 -> User defined) Opcode Bits(2) 1 1 1 A7 A6 A1 A0 Busy Ready tWP Address Bits(8) CS SK DI DO High - Z tCS ERASE ALL CYCLE (ERAL) Start Bit 93C56: Address bits pattern -> 1-0-x-x-x-x-x-x ; (x -> Don ’ t Care, can be 0 or 1) Opcode Bits(2) 1 0 0 A7 A6 A1 A0 Busy Ready tWP |
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