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FM93CS06 Rev. C.1

CS

SK

DI

DO

High - Z

Dummy

Bit

1

1

0

A5

A4

A1

A0

PRE

PE

0

D5

D1

D0

;;;;;;;;;;;;;;

;;;;;;;;;;;;;;

;;;;

;;;;

;;;

;;;

PROTECT REGISTER READ CYCLE (PRREAD)

Address

Bits(6)

Star t

Bit

Opcode

Bits(2)

93CS06:

Address bits patter n -> x-x-x-x-x-x; (x -> Don't Care, can be 0 or 1)

Of the 6-bit output data(D5-D0), only D3 to D0 are valid and they correspond to A3 to A0 respectively.

;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;

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Address

Bits(6)

CS

PE

SK

DI

DO

High - Z

PROTECT REGISTER ENABLE CYCLE (PREN)

Star t

Bit

93CS06:

Address bits patter n -> 1-1-x-x-x-x; (x -> Don't Care, can be 0 or 1)

Opcode

Bits(2)

1

0

0

A5

A4

A1

A0

PRE

;;;;;;;;;

;;;;;;;;;

;;;;;;;;;

;;;;;;;;;

Address

Bits(6)

Data

Bits(16)

CS

PE

SK

DI

DO

High - Z

WRITE ALL CYCLE (WRALL)

Star t

Bit

93CS06:

Address bits patter n -> 0-1-x-x-x-x; (x -> Don't Care, can be 0 or 1)

Data bits patter n

-> User defined

Opcode

Bits(2)

1

0

0

A5

A4

A1

A0

D15

D14

D1

D0

PRE

Busy

Ready