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Am79C940B-25JC 데이터시트(PDF) 2 Page - Rochester Electronics |
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2 / 13 page 79C940 Specification Number 79C940B-CI (A) Rev C Page 2 of 13 2 Am79C940 The MACE device provides a complete Ethernet node solution with an integrated 10BASE-T transceiver, and supports up to 25-MHz system clocks. The MACE device embodies the Media Access Control (MAC) and Physical Signaling (PLS) sub-layers of the IEEE 802.3 standard, and provides an IEEE defined Attach- ment Unit Interface (AUI) for coupling to an external Medium Attachment Unit (MAU). The MACE device is compliant with 10BASE2, 10BASE5, 10BASE-T, and 10BASE-F transceivers. Additional features also enhance over-all system design. The individual transmit and receive FIFOs optimize system overhead, providing substantial latency during packet transmission and reception, and minimizing intervention during normal network error recovery. The integrated Manchester encoder/decoder eliminates the need for an external Serial Interface Adapter (SIA) in the node system. If support for an external encoding/decoding scheme is desired, the General Purpose Serial Interface (GPSI) allows direct access to/from the MAC. In addition, the Digital Attach- ment Interface (DAI), which is a simplified electrical attachment specification, allows implementation of MAUs that do not require DC isolation between the MAU and DTE. The DAI port can also be used to indicate transmit, receive, or collision status by connecting LEDs to the port. The MACE device also provides an External Address Detection Interface (EADI) to allow external hardware address filtering in internet working applications. The Am79C940 MACE chip is offered in a Plastic Leadless Chip Carrier (84-pin PLCC), a Plastic Quad Flat Package (100-pin PQFP), and a Thin Quad Flat Package (TQFP 80-pin). There are several small func- tional and physical differences between the 80-pin TQFP and the 84-pin PLCC and 100-pin PQFP config- urations. Because of the smaller number of pins in the TQFP configuration versus the PLCC configuration, four pins are not bonded out. Though the die is identical in all three package configurations, the removal of these four pins does cause some functionality differ- ences between the TQFP and the PLCC and PQFP configurations. Depending on the application, the removal of these pins will or will not have an effect. (See section: “Pins Removed for TQFP Package and Their Effects.) With the rise of embedded networking applications op- erating in harsh environments where temperatures may exceed the normal commercial temperature (0°C to +70°C) window, an industrial temperature (-40°C to +85°C) version is available in all three packages; 84- pin PLCC, 100-pin PQFP and 80-pin TQFP. The indus- trial temperature version of the MACE Ethernet control- ler is characterized across the industrial temperature range (-40°C to +85°C) within the published power supply specification (4.75 V to 5.25 V; i.e., ±5% VCC). Thus, conformance of MACE performance over this temperature range is guaranteed by the design and characterization monitor. TABLE 5 SPECIFICATION NUMBER: 79C940-CI (A) REV - Page 2 of 13 2 Am79C940 The MACE device provides a complete Ethernet node solution with an integrated 10BASE-T transceiver, and supports up to 25-MHz system clocks. The MACE device embodies the Media Access Control (MAC) and Physical Signaling (PLS) sub-layers of the IEEE 802.3 standard, and provides an IEEE defined Attach- ment Unit Interface (AUI) for coupling to an external Medium Attachment Unit (MAU). The MACE device is compliant with 10BASE2, 10BASE5, 10BASE-T, and 10BASE-F transceivers. Additional features also enhance over-all system design. The individual transmit and receive FIFOs optimize system overhead, providing substantial latency during packet transmission and reception, and minimizing intervention during normal network error recovery. The integrated Manchester encoder/decoder eliminates the need for an external Serial Interface Adapter (SIA) in the node system. If support for an external encoding/decoding scheme is desired, the General Purpose Serial Interface (GPSI) allows direct access to/from the MAC. In addition, the Digital Attach- ment Interface (DAI), which is a simplified electrical attachment specification, allows implementation of MAUs that do not require DC isolation between the MAU and DTE. The DAI port can also be used to indicate transmit, receive, or collision status by connecting LEDs to the port. The MACE device also provides an External Address Detection Interface (EADI) to allow external hardware address filtering in internet working applications. The Am79C940 MACE chip is offered in a Plastic Leadless Chip Carrier (84-pin PLCC), a Plastic Quad Flat Package (100-pin PQFP), and a Thin Quad Flat Package (TQFP 80-pin). There are several small func- tional and physical differences between the 80-pin TQFP and the 84-pin PLCC and 100-pin PQFP config- urations. Because of the smaller number of pins in the TQFP configuration versus the PLCC configuration, four pins are not bonded out. Though the die is identical in all three package configurations, the removal of these four pins does cause some functionality differ- ences between the TQFP and the PLCC and PQFP configurations. Depending on the application, the removal of these pins will or will not have an effect. (See section: “Pins Removed for TQFP Package and Their Effects.) With the rise of embedded networking applications op- erating in harsh environments where temperatures may exceed the normal commercial temperature (0°C to +70°C) window, an industrial temperature (-40°C to +85°C) version is available in all three packages; 84- pin PLCC, 100-pin PQFP and 80-pin TQFP. The indus- trial temperature version of the MACE Ethernet control- ler is characterized across the industrial temperature range (-40°C to +85°C) within the published power supply specification (4.75 V to 5.25 V; i.e., ±5% VCC). Thus, conformance of MACE performance over this temperature range is guaranteed by the design and characterization monitor. TABLE 5 SPECIFICATION NUMBER: 79C940-CI (A) REV - Page 2 of 13 FINAL Publication# 16235 Rev: E Amendment/0 Issue Date: May 2000 Am79C940 Media Access Controller for Ethernet (MACE™) DISTINCTIVE CHARACTERISTICS Integrated Controller with Manchester encoder/decoder and 10BASE-T transceiver and AUI port Supports IEEE 802.3/ANSI 8802-3 and Ethernet standards 84-pin PLCC and 100-pin PQFP Packages 80-pin Thin Quad Flat Pack (TQFP) package available for space critical applications such as PCMCIA Modular architecture allows easy tuning to specific applications High speed, 16-bit synchronous host system interface with 2 or 3 cycles/transfer Individual transmit (136 byte) and receive (128 byte) FlFOs provide increase of system latency and support the following features: — Automatic retransmission with no FIFO reload — Automatic receive stripping and transmit padding (individually programmable) — Automatic runt packet rejection — Automatic deletion of collision frames — Automatic retransmission with no FIFO reload Direct slave access to all on board configuration/status registers and transmit/ receive FlFOs Direct FIFO read/write access for simple interface to DMA controllers or l/O processors Arbitrary byte alignment and little/big endian memory interface supported Internal/external loopback capabilities External Address Detection Interface (EADI) for external hardware address filtering in bridge/router applications JTAG Boundary Scan (IEEE 1149.1) test access port interface for board level production test Integrated Manchester Encoder/Decoder Digital Attachment Interface (DAI) allows by-passing of differential Attachment Unit Interface (AUI) Supports the following types of network interface: — AUI to external 10BASE2, 10BASE5 or 10BASE-F MAU — DAI port to external 10BASE2, 10BASE5, 10BASE-T, 10BASE-F MAU — General Purpose Serial Interface (GPSI) to external encoding/decoding scheme — Internal 10BASE-T transceiver with automatic selection of 10BASE-T or AUI port Sleep mode allows reduced power consump- tion for critical battery powered applications 5 MHz-25 MHz system clock speed Support for operation in industrial temperature range (–40°C to +85°C) available in all three packages GENERAL DESCRIPTION The Media Access Controller for Ethernet (MACE) chip is a CMOS VLSI device designed to provide flexibility in customized LAN design. The MACE device is specif- ically designed to address applications where multiple I/O peripherals are present, and a centralized or sys- tem specific DMA is required. The high speed, 16-bit synchronous system interface is optimized for an exter- nal DMA or I/O processor system, and is similar to many existing peripheral devices, such as SCSI and serial link controllers. The MACE device is a slave register based peripheral. All transfers to and from the system are performed using simple memory or I/O read and write commands. In conjunction with a user defined DMA engine, the MACE chip provides an IEEE 802.3 interface tailored to a specific application. Its superior modular architec- ture and versatile system interface allow the MACE device to be configured as a stand-alone device or as a connectivity cell incorporated into a larger, integrated system. TABLE 5 SPECIFICATION NUMBER: 79C940-CI (A) REV - Page 1 of 13 FINAL Publication# 16235 Rev: E Amendment/0 Issue Date: May 2000 Am79C940 Media Access Controller for Ethernet (MACE™) DISTINCTIVE CHARACTERISTICS Integrated Controller with Manchester encoder/decoder and 10BASE-T transceiver and AUI port Supports IEEE 802.3/ANSI 8802-3 and Ethernet standards 84-pin PLCC and 100-pin PQFP Packages 80-pin Thin Quad Flat Pack (TQFP) package available for space critical applications such as PCMCIA Modular architecture allows easy tuning to specific applications High speed, 16-bit synchronous host system interface with 2 or 3 cycles/transfer Individual transmit (136 byte) and receive (128 byte) FlFOs provide increase of system latency and support the following features: — Automatic retransmission with no FIFO reload — Automatic receive stripping and transmit padding (individually programmable) — Automatic runt packet rejection — Automatic deletion of collision frames — Automatic retransmission with no FIFO reload Direct slave access to all on board configuration/status registers and transmit/ receive FlFOs Direct FIFO read/write access for simple interface to DMA controllers or l/O processors Arbitrary byte alignment and little/big endian memory interface supported Internal/external loopback capabilities External Address Detection Interface (EADI) for external hardware address filtering in bridge/router applications JTAG Boundary Scan (IEEE 1149.1) test access port interface for board level production test Integrated Manchester Encoder/Decoder Digital Attachment Interface (DAI) allows by-passing of differential Attachment Unit Interface (AUI) Supports the following types of network interface: — AUI to external 10BASE2, 10BASE5 or 10BASE-F MAU — DAI port to external 10BASE2, 10BASE5, 10BASE-T, 10BASE-F MAU — General Purpose Serial Interface (GPSI) to external encoding/decoding scheme — Internal 10BASE-T transceiver with automatic selection of 10BASE-T or AUI port Sleep mode allows reduced power consump- tion for critical battery powered applications 5 MHz-25 MHz system clock speed Support for operation in industrial temperature range (–40°C to +85°C) available in all three packages GENERAL DESCRIPTION The Media Access Controller for Ethernet (MACE) chip is a CMOS VLSI device designed to provide flexibility in customized LAN design. The MACE device is specif- ically designed to address applications where multiple I/O peripherals are present, and a centralized or sys- tem specific DMA is required. The high speed, 16-bit synchronous system interface is optimized for an exter- nal DMA or I/O processor system, and is similar to many existing peripheral devices, such as SCSI and serial link controllers. The MACE device is a slave register based peripheral. All transfers to and from the system are performed using simple memory or I/O read and write commands. In conjunction with a user defined DMA engine, the MACE chip provides an IEEE 802.3 interface tailored to a specific application. Its superior modular architec- ture and versatile system interface allow the MACE device to be configured as a stand-alone device or as a connectivity cell incorporated into a larger, integrated system. TABLE 5 SPECIFICATION NUMBER: 79C940-CI (A) REV - Page 1 of 13 The 79C940 MACE chip is offered in a Plastic |
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