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AD5625RACPZ-REEL7 데이터시트(PDF) 9 Page - Analog Devices

부품명 AD5625RACPZ-REEL7
상세설명  Quad, 12-/14-/16-Bit nanoDACs with 5 ppm/째C On-Chip Reference, I2C Interface
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AD5625RACPZ-REEL7 데이터시트(HTML) 9 Page - Analog Devices

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Data Sheet
AD5625R/AD5645R/AD5665R, AD5625/AD5665
Rev. C | Page 9 of 36
Parameter
Test Conditions2
Min
Max
Unit
Description
t12
Standard mode
300
ns
tFCL, fall time of SCL signal
Fast mode
300
ns
High speed mode, CB = 100 pF
10
40
ns
High speed mode, CB = 400 pF
20
80
ns
t13
Standard mode
10
ns
LDAC pulse width low
Fast mode
10
ns
High speed mode
10
ns
t14
Standard mode
300
ns
Falling edge of ninth SCL clock pulse of last byte
of a valid write to LDAC falling edge
Fast mode
300
ns
High speed mode
30
ns
t15
Standard mode
20
ns
CLR pulse width low
Fast mode
20
ns
High speed mode
20
ns
tSP4
Fast mode
0
50
ns
Pulse width of spike suppressed
High speed mode
0
10
ns
1
See Figure 3. High speed mode timing specification applies only to the AD5625RBRUZ-2/AD5625RBRUZ-2REEL7 and AD5665RBRUZ-2/AD5665RBRUZ-2REEL7.
2
CB refers to the capacitance on the bus line.
3
The SDA and SCL timing is measured with the input filters enabled. Switching off the input filters improves the transfer rate but has a negative effect on the EMC
behavior of the part.
4
Input filtering on the SCL and SDA inputs suppresses noise spikes that are less than 50 ns for fast mode or less than 10 ns for high speed mode.
Figure 3. 2-Wire Serial Interface Timing Diagram
SCL
SDA
P
S
S
P
t8
t6
t5
t3
t10
t9
t4
t6
t1
t2
t11
t12
t14
CLR
t13
t15
LDAC*
t7
*ASYNCHRONOUS LDAC UPDATE MODE.


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