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FAN4800AUN 데이터시트(PDF) 9 Page - Fairchild Semiconductor |
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FAN4800AUN 데이터시트(HTML) 9 Page - Fairchild Semiconductor |
9 / 20 page © 2011 Fairchild Semiconductor Corporation www.fairchildsemi.com FAN4800AU/CU • Rev. 1.0.0 9 Electrical Characteristics (Continued) Unless otherwise noted, VDD=15V, TA= 25°C, TA=TJ, RT=6.8kΩ, and CT=1000pF. Symbol Parameter Condition Min. Typ. Max. Unit PFC Output Driver VGATE-CLAMP Gate Output Clamping Voltage VDD=22V 13 15 17 V VGATE-L Gate Low Voltage VDD=15V, IO=100mA 1.5 V VGATE-H Gate High Voltage VDD=13V, IO=100mA 8 V tR Gate Rising Time VDD=15V, CL=4.7nF, O/P= 2V to 9V 40 70 120 ns tF Gate Falling Time VDD=15V, CL=4.7nF, O/P=9V to 2V 40 60 110 ns DPFC-MAX Maximum Duty Cycle VIEA<1.2V 94 97 % DPFC-MIN Minimum Duty Cycle VIEA>4.5V 0 % PWM ILIMIT Comparator VPWM-ILIMIT Threshold Voltage 0.95 1.00 1.05 V tPD Propagation Delay to Output 250 ns tPWM-BNK Leading-Edge Blanking Time 170 250 350 ns PWM Output Driver VGATE-CLAMP Gate Output Clamping Voltage VDD=22V 18 19 20 V VGATE-L Gate Low Voltage VDD=15V, IO=100mA 1.5 V VGATE-H Gate High Voltage VDD=13V, IO=100mA 8 V tR Gate Rising Time VDD=15V, CL=4.7nF, O/P=2V to 9V 30 60 120 ns tF Gate Falling Time VDD=15V, CL=4.7nF, O/P=9V to 2V 30 50 110 ns DPWM-MAX Maximum Duty Cycle 49.0 49.5 50.0 % VPWM-LS PWM Comparator Level Shift 1.3 1.5 1.8 V Soft-Start VSS-MAX Maximum Voltage VDD=15V 9.5 10.0 10.5 V ISS Soft-Start Current 10 µA Brownout VRMS-UVL VRMS Threshold LOW 1.00 1.05 1.10 V VRMS-UVH VRMS Threshold HIGH 1.85 1.90 1.95 V △ VRMS-UVP Hysteresis 750 850 950 mV tUVP Under- Voltage Protection Delay 750 1000 1250 ms Sagging Protection VRMS-SAG VRMS Threshold SAG LOW 0.80 0.85 0.90 V tSAG SAG Protection Delay 28 33 38 ms Notes: 3. This parameter, although guaranteed by design, is not 100% production tested. 4. This gain is the maximum gain of modulation with a given VRMS voltage when VVEA is saturated to HIGH. |
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