Micrel, Inc.

KSZ9021RL/RN

October 2009

6

M9999-101309-1.1

List of Figures

Figure 1. KSZ9021RL/RN Block Diagram............................................................................................................................ 22

Figure 2: KSZ9021RL/RN 1000Base-T Block Diagram – Single Channel .......................................................................... 24

Figure 3: Auto-Negotiation Flow Chart................................................................................................................................. 27

Figure 4: KSZ9021RL/RN RGMII Interface.......................................................................................................................... 29

Figure 5. RGMII v1.3 Specification (Figure 2 – Multiplexing & Timing Diagram) ................................................................ 48

Figure 6. Auto-Negotiation Fast Link Pulse (FLP) Timing ................................................................................................... 49

Figure 7. MDC/MDIO Timing................................................................................................................................................ 50

Figure 8. Reset Timing......................................................................................................................................................... 51

Figure 9. Recommended Reset Circuit................................................................................................................................ 51

Figure 10. Recommended Reset Circuit for Interfacing with CPU/FPGA Reset Output ..................................................... 52

Figure 11. Reference Circuits for LED Strapping Pins......................................................................................................... 52

Figure 12. 25MHz Crystal / Oscillator Reference Clock Connection ................................................................................... 53