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MCZ33937AEK 데이터시트(PDF) 10 Page - Freescale Semiconductor, Inc |
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MCZ33937AEK 데이터시트(HTML) 10 Page - Freescale Semiconductor, Inc |
10 / 48 page Analog Integrated Circuit Device Data 10 Freescale Semiconductor 33937A ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS OVER-CURRENT COMPARATOR Common Mode Input Range(22) VCM 2.0 – VDD-0.02 V Input Offset Voltage VOS_OC -50 – 50 mV Over-current Comparator Threshold Hysteresis(21) VOC_HYST 50 300 mV Output Voltage High Level at IOH = -500 µA Low Level at IOL = 500 µA VOH VOL 0.85 VDD – – – VDD 0.5 V HOLD OFF CIRCUIT Hold Off Current (At Each GATE Pin) 3.0 V < VSUP < 40 V, VGATE = 1.0 V(23) IHOLD 10 – 300 µA PHASE COMPARATOR High Level Input Voltage Threshold VIH_TH 0.5 VSUP – 0.65 VSUP V Low Level Input Voltage Threshold VIL_TH 0.3 VSUP – 0.45 VSUP V High Level Output Voltage at IOH = -500 µA VOH 0.85 VDD – VDD V Low Level Output Voltage at IOL = 500 µA VOL – – 0.5 V High Side Source Input Resistance(21), (26) RIN – 40 – k DESATURATION DETECTOR Desaturation Detector Threshold(24) VDES_TH 1.2 1.4 1.6 V CURRENT SENSE AMPLIFIER Recommended External Series Resistor (See Figure 9) RS – 1.0 – k Recommended External Feedback Resistor (See Figure 9)(27) Limited by the Output Voltage Dynamic Range RFB 5.0 – 15 k Maximum Input Differential Voltage (See Figure 9) VID = VAMP_P - VAMP_N VID -800 – +800 mV Input Common Mode Range(21), (25) VCM -0.5 – 3.0 V Input Offset Voltage RS = 1.0 k, VCM = 0.0 V VOS -15 – +15 mV Input Offset Voltage Drift(21) VOS/T – -10 – µV/°C Input Bias Current VCM = 2.0 V Ib -200 – +200 nA Notes 21. This parameter is a design characteristic, not production tested. 22. As long as one input is in the common mode range there is no phase inversion on the output. 23. The hold off circuit is designed to operate over the full operating range of VSUP. The specification indicates the conditions used in production test. Hold off is activated at VPOR or VTHVLS. 24. Desaturation is measured as the voltage drop below VSUP, thus the threshold is compared to the drain-source voltage of the external High Side FET. See Figure 5. 25. As long as one input is within VCM the output is guaranteed to have the correct phase. Exceeding the common mode rails on one input will not cause a phase inversion on the output. 26. Input resistance is impedance from the high side source and is referenced to VSS. Approximate tolerance is 20 27. The current sense amplifier is unity gain stable with a phase margin of approximately 45°. See Figure 10. Table 3. Static Electrical Characteristics (continued) Characteristics noted under conditions 8.0 V VPWR = VSUP 40 V-40 C TA 135 C, unless otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25 °C under nominal conditions, unless otherwise noted. Characteristic Symbol Min Typ Max Unit |
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