전자부품 데이터시트 검색엔진 |
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Si5324A-C-GM 데이터시트(PDF) 9 Page - Silicon Laboratories |
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Si5324A-C-GM 데이터시트(HTML) 9 Page - Silicon Laboratories |
9 / 72 page Si5324 Rev. 1.0 9 Table 3. AC Characteristics (VDD = 1.8 ± 5%, 2.5 ±10%, or 3.3 V ±10%, TA = –40 to 85 °C) Parameter Symbol Test Condition Min Typ Max Unit Single-Ended Reference Clock Input Pin XA (XB with cap to GND) Input Resistance XARIN RATE[1:0] = LM, ML, MH, or HM, ac coupled —12 — k Input Voltage Swing XAVPP RATE[1:0] = LM, ML, MH, or HM, ac coupled 0.5 — 1.2 VPP Differential Reference Clock Input Pins (XA/XB) Input Voltage Swing XA/XBVPP RATE[1:0] = LM, ML, MH, or HM 0.5 — 2.4 VPP CKINn Input Pins Input Frequency CKNF 0.002 — 710 MHz Input Duty Cycle (Minimum Pulse Width) CKNDC Whichever is smaller (i.e., the 40% / 60% limitation applies only to high frequency clocks) 40 — 60 % 2— — ns Input Capacitance CKNCIN —— 3 pF Input Rise/Fall Time CKNTRF 20–80% See Figure 2 —— 11 ns CKOUTn Output Pins (See ordering section for speed grade vs frequency limits) Output Frequency (Output not configured for CMOS or Disabled) CKOF N1 60.002 — 945 MHz N1 = 5 970 — 1134 MHz N1 = 4 1.213 — 1.4 GHz Maximum Output Frequency in CMOS Format CKOF — — 212.5 MHz Notes: 1. Input to output phase skew after an ICAL is not controlled and can assume any value. 2. Lock and settle time performance is dependent on the frequency plan and the XAXB reference frequency. Please visit the Silicon Labs Technical Support web page at: https://www.silabs.com/support/pages/contacttechnicalsupport.aspx to submit a technical support request regarding the lock time of your frequency plan. |
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