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SI8440AB-D-IS 데이터시트(PDF) 7 Page - Silicon Laboratories |
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SI8440AB-D-IS 데이터시트(HTML) 7 Page - Silicon Laboratories |
7 / 38 page Si8440/41/42/45 Rev. 1.5 7 Si844xBx Maximum Data Rate 0 — 150 Mbps Minimum Pulse Width — — 6.0 ns Propagation Delay tPHL, tPLH See Figure 2 3.0 6.0 9.5 ns Pulse Width Distortion |tPLH - tPHL| PWD See Figure 2 — 1.5 2.5 ns Propagation Delay Skew2 tPSK(P-P) —2.0 3.0 ns Channel-Channel Skew tPSK —0.5 1.8 ns All Models Output Rise Time tr CL =15pF See Figure 2 —3.8 5.0 ns Output Fall Time tf CL =15pF See Figure 2 —2.8 3.7 ns Common Mode Transient Immunity CMTI VI =VDD or 0 V — 25 — kV/µs Enable to Data Valid3 ten1 See Figure 1 — 5.0 8.0 ns Enable to Data Tri-State3 ten2 See Figure 1 — 7.0 9.2 ns Start-up Time3,4 tSU —15 40 µs Table 3. Electrical Characteristics (Continued) (VDD1 = 5 V ±10%, VDD2 = 5 V ±10%, TA = –40 to 125 ºC; applies to narrow and wide-body SOIC packages) Parameter Symbol Test Condition Min Typ Max Unit Notes: 1. The nominal output impedance of an isolator driver channel is approximately 85 , ±40%, which is a combination of the value of the on-chip series termination resistor and channel resistance of the output driver FET. When driving loads where transmission line effects will be a factor, output pins should be appropriately terminated with controlled impedance PCB traces. 2. tPSK(P-P) is the magnitude of the difference in propagation delay times measured between different units operating at the same supply voltages, load, and ambient temperature. 3. See "3. Errata and Design Migration Guidelines" on page 25 for more details. 4. Start-up time is the time period from the application of power to valid data at the output. |
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