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Si5326A-C-GM 데이터시트(PDF) 8 Page - Silicon Laboratories |
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Si5326A-C-GM 데이터시트(HTML) 8 Page - Silicon Laboratories |
8 / 72 page Si5326 8 Rev. 1.0 3-Level Input Pins4 Input Voltage Low VILL — — 0.15 x VDD V Input Voltage Mid VIMM 0.45 x VDD —0.55 x VDD V Input Voltage High VIHH 0.85 x VDD —— V Input Low Current IILL See Note 4 –20 — — µA Input Mid Current IIMM See Note 4 –2 — +2 µA Input High Current IIHH See Note 4 — — 20 µA LVCMOS Output Pins Output Voltage Low VOL IO = 2 mA VDD =1.71V —— 0.4 V Output Voltage Low IO = 2 mA VDD =2.97V —— 0.4 V Output Voltage High VOH IO = –2 mA VDD =1.71V VDD – 0.4 —— V Output Voltage High IO = –2 mA VDD =2.97V VDD – 0.4 —— V Disabled Leakage Current IOZ RSTb = 0 –100 — 100 µA Table 2. DC Characteristics (Continued) (VDD = 1.8 ± 5%, 2.5 ±10%, or 3.3 V ±10%, TA = –40 to 85 °C) Parameter Symbol Test Condition Min Typ Max Unit Notes: 1. Current draw is independent of supply voltage 2. No under- or overshoot is allowed. 3. LVPECL outputs require nominal VDD ≥ 2.5 V. 4. This is the amount of leakage that the 3-Level inputs can tolerate from an external driver. See Si53xx Family Reference Manual for more details. 5. LVPECL, CML, LVDS and low-swing LVDS measured with Fo = 622.08 MHz. |
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