전자부품 데이터시트 검색엔진 |
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SI5013-D-GM 데이터시트(PDF) 9 Page - Silicon Laboratories |
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SI5013-D-GM 데이터시트(HTML) 9 Page - Silicon Laboratories |
9 / 26 page Si5013 Rev. 1.6 9 Table 4. AC Characteristics (PLL Characteristics) (VDD = 3.3 V ±5%, TA = –40 to 85 °C) Parameter Symbol Test Condition Min Typ Max Unit Jitter Tolerance (OC-12 Mode)* JTOL(PP) f = 30 Hz 60 — — UIPP f=300Hz 6 — — UIPP f= 25 kHz 4 — — UIPP f = 250 kHz 0.4 — — UIPP Jitter Tolerance (OC-3 Mode)* JTOL(PP) f = 30 Hz 60 — — UIPP f=300Hz 6 — — UIPP f=6.5 kHz 4 — — UIPP f= 65 kHz 0.4 — — UIPP RMS Jitter Generation* JGEN(rms) with no jitter on serial data — 2.3 4.0 mUI Peak-to-Peak Jitter Generation* JGEN(PP) with no jitter on serial data — 20 45 mUI Jitter Transfer Bandwidth* JBW OC-12 Mode — — 500 kHz OC-3 Mode — — 130 kHz Jitter Transfer Peaking* JP —0.03 0.1 dB Acquisition Time—OC-12 (Reference clock applied) TAQ After falling edge of PWRDN/CAL —1.5 2 ms From the return of valid data —60 — µs Acquisition Time—OC-12 (Reference-less operation) TAQ After falling edge of PWRDN/CAL —4.0 12 ms From the return of valid data —13 — ms Reference Clock Range See "4.4. Operation Without an External Ref- erence" on page 12. 155.5 77.76 19.44 MHz Input Reference Clock Frequency Tolerance CTOL –500 — 500 ppm Frequency Difference at which Receive PLL goes out of Lock (REFCLK compared to the divided down VCO clock) —±650 — ppm *Note: As defined in Bellcore specifications: GR-253-CORE, Issue 3, September 2000. Using PRBS 223 – 1 data pattern. |
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