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ADC101S051CIMF 데이터시트(PDF) 2 Page - TEXAS ADVANCED OPTOELECTRONIC SOLUTIONS |
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2 / 16 page Block Diagram 20144707 Pin Descriptions and Equivalent Circuits Pin No. Symbol Description ANALOG I/O 3V IN Analog input. This signal can range from 0V to V A. DIGITAL I/O 4 SCLK Digital clock input. This clock directly controls the conversion and readout processes. 5 SDATA Digital data output. The output samples are clocked out of this pin on falling edges of the SCLK pin. 6CS Chip select. On the falling edge of CS, a conversion process begins. POWER SUPPLY 1V A Positive supply pin. This pin should be connected to a quiet +2.7V to +5.25V source and bypassed to GND witha1µF capacitor and a 0.1 µF monolithic capacitor located within 1 cm of the power pin. 2 GND The ground return for the supply and signals. PAD GND For package suffix CISD(X) only, it is recommended that the center pad should be connected to ground. www.national.com 2 |
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