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AD5314BCPZ-REEL7 데이터시트(PDF) 7 Page - Analog Devices |
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AD5314BCPZ-REEL7 데이터시트(HTML) 7 Page - Analog Devices |
7 / 24 page Data Sheet AD5304/AD5314/AD5324 Rev. H | Page 7 of 24 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS VDD 1 VOUTA 2 VOUTB 3 VOUTC 4 REFIN 5 AD5304/ AD5314/ AD5324 TOP VIEW (Not to Scale) SYNC 10 SCLK 9 DIN 8 GND 7 VOUTD 6 Figure 3. 10-Lead MSOP Pin Configuration VDD VOUTA VOUTB VOUTC REFIN AD5304/ AD5314/ AD5324 NOTES 1. THE EXPOSED PAD IS THE GROUND REFERENCE POINT FOR ALL CIRCUITRY ON THE PART. IT CAN BE CONNECTED TO 0 V OR LEFT UNCONNECTED PROVIDED THERE IS A CONNECTION TO 0 V VIA THE GND PIN. TOP VIEW (Not to Scale) SCLK DIN GND VOUTD SYNC 1 2 3 4 5 10 9 8 7 6 Figure 4. 10-Lead LFCSP Pin Configuration Table 5. Pin Function Descriptions Pin No. Mnemonic Description 1 VDD Power Supply Input. These parts can be operated from 2.5 V to 5.5 V and the supply can be decoupled to GND. 2 VOUTA Buffered Analog Output Voltage from DAC A. The output amplifier has rail-to-rail operation. 3 VOUTB Buffered Analog Output Voltage from DAC B. The output amplifier has rail-to-rail operation. 4 VOUTC Buffered Analog Output Voltage from DAC C. The output amplifier has rail-to-rail operation. 5 REFIN Reference Input Pin for All Four DACs. It has an input range from 0.25 V to VDD. 6 VOUTD Buffered Analog Output Voltage from DAC D. The output amplifier has rail-to-rail operation. 7 GND Ground Reference Point for All Circuitry on the Part. 8 DIN Serial Data Input. This device has a 16-bit shift register. Data is clocked into the register on the falling edge of the serial clock input. The DIN input buffer is powered down after each write cycle. 9 SCLK Serial Clock Input. Data is clocked into the input shift register on the falling edge of the serial clock input. Data can be transferred at clock speeds up to 30 MHz. The SCLK input buffer is powered down after each write cycle. 10 SYNC Active Low Control Input. This is the frame synchronization signal for the input data. When SYNC goes low, it enables the input shift register and data is transferred in on the falling edges of the following 16 clocks. If SYNC is taken high before the 16th falling edge of SCLK, the rising edge of SYNC acts as an interrupt and the write sequence is ignored by the device. Exposed Paddle1 Ground Reference Point for All Circuitry on the Part. Can be connected to 0 V or left unconnected provided there is a connection to 0 V via the GND pin. 1 For the 10-Lead LFCSP only. |
유사한 부품 번호 - AD5314BCPZ-REEL7 |
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유사한 설명 - AD5314BCPZ-REEL7 |
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