전자부품 데이터시트 검색엔진 |
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Si5328C-C-GM 데이터시트(PDF) 9 Page - Silicon Laboratories |
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Si5328C-C-GM 데이터시트(HTML) 9 Page - Silicon Laboratories |
9 / 70 page Si5328 Rev. 1.0 9 Table 3. AC Characteristics (VDD = 2.5 ±10% or 3.3 V ±10%, TA = –40 to 85 °C) Parameter Symbol Test Condition Min Typ Max Unit Single-Ended Reference Clock Input Pin XA (XB with cap to GND) Input Resistance XARIN RATE[1:0] = LM, ML, MH, ac coupled —12 — k Input Voltage Swing XAVPP RATE[1:0] = LM, ML, MH, ac coupled 0.5 — 1.2 VPP Differential Reference Clock Input Pins (XA/XB) Input Voltage Swing XA/XBVPP RATE[1:0] = LM, ML, MH 0.5 — 1.2 VPP, each. CKINn Input Pins Input Frequency CKNF 0.008 — 710 MHz Input Duty Cycle (Minimum Pulse Width) CKNDC Input frequency > 225 MHz 40 — 60 % Input frequency < 225 MHz refers to both high and low widths 2— — ns Input Capacitance CKNCIN —— 3 pF Input Rise/Fall Time CKNTRF 20–80% See Figure 2 —— 11 ns CKOUTn Output Pins (See ordering section for speed grade vs frequency limits) Output Frequency (Output not config- ured for CMOS) CKOF N1 6 0.008 — 808 MHz Maximum Output Frequency in CMOS Format CKOF — — 212.5 MHz Output Rise/Fall (20–80%) @ 212.5 MHz output CKOTRF CMOS Output VDD =2.25 CLOAD =5pF —— 8 ns Output Rise/Fall (20–80%) @ 212.5 MHz output CKOTRF CMOS Output VDD =2.97 CLOAD =5pF —— 2 ns Notes: 1. Lock and settle times may change with different f3, loop BW, and VCO frequency values. Contact Silicon Labs for further details. 2. See Section 9 of “AN775: Si5328 Synchronous Ethernet Compliance Test Report” for more details. |
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