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74ABT125 데이터시트(PDF) 6 Page - NXP Semiconductors |
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74ABT125 데이터시트(HTML) 6 Page - NXP Semiconductors |
6 / 15 page 74ABT125_4 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 04 — 27 April 2010 6 of 15 NXP Semiconductors 74ABT125 Quad buffer; 3-state VM =1.5 V VOL and VOH are typical voltage output levels that occur with the output load. Fig 7. Enable and disable times 001aal294 tPLZ tPHZ outputs disabled outputs enabled VOH − 0.3 V VOL + 0.3 V outputs enabled output LOW-to-OFF OFF-to-LOW output HIGH-to-OFF OFF-to-HIGH nOE input VI VOL VOH 3.5 V VM VM GND GND tPZL tPZH VM VM a. Input pulse definition b. Test circuit Test data is given in Table 8. Test circuit definitions: RL = Load resistance. CL = Load capacitance including jig and probe capacitance. RT = Termination resistance should be equal to output impedance Zo of the pulse generator. VEXT = Test voltage for switching times. Fig 8. Load circuitry for switching times 001aai298 VM VM tW tW 10 % 90 % 90 % 0 V VI VI negative pulse positive pulse 0 V VM VM 90 % 10 % 90 % 10 % 10 % tf tr tr tf VEXT VCC VI VO mna616 DUT CL RT RL RL G Table 8. Test data Input Load VEXT VI fI tW tr, tf CL RL tPHL, tPLH tPZH, tPHZ tPZL, tPLZ 3.0 V 1 MHz 500 ns ≤ 2.5 ns 50 pF 500 Ω open open 7.0 V |
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