전자부품 데이터시트 검색엔진 |
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KM4212 데이터시트(PDF) 7 Page - Fairchild Semiconductor |
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KM4212 데이터시트(HTML) 7 Page - Fairchild Semiconductor |
7 / 10 page REV. 1 August 2001 7 Layout Considerations General layout and supply bypassing play major roles in high frequency performance. Fairchild has evaluation boards to use as a guide for high frequency layout and to aid in device testing and characterization. Follow the steps below as a basis for high frequency layout: I Include 6.8 µF and 0.01µF ceramic capacitors I Place the 6.8 µF capacitor within 0.75 inches of the power pin I Place the 0.01 µF capacitor within 0.1 inches of the power pin I Remove the ground plane under and around the part, especially near the input and output pins to reduce parasitic capacitance I Minimize all trace lengths to reduce series inductances Refer to the evaluation board layouts shown in Figure 6 for more information. When evaluating only one channel, complete the following on the unused channel 1. Ground the non-inverting input 2. Short the output to the inverting input Evaluation Board Information The following evaluation boards are available to aid in the testing and layout of this device: Evaluation board schematics and layouts are shown in Figure 5 and Figure 6. The KEB002 evaluation board is built for dual supply operation. Follow these steps to use the board in a single supply application: 1. Short -Vs to ground 2. Use C3 and C4, if the -Vs pin of the KM4212 is not directly connected to the ground plane. Figure 5: Evaluation Board Schematic KM4212 DATA SHEET Eval Board Description Products KEB006 Dual Channel, KM4212IC8 Dual Supply 8 lead SOIC KEB010 Dual Channel, KM4212IM8 Dual Supply 8 lead MSOP |
유사한 부품 번호 - KM4212 |
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유사한 설명 - KM4212 |
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