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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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FAN6754WAMRMY 데이터시트(PDF) 11 Page - Fairchild Semiconductor |
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FAN6754WAMRMY 데이터시트(HTML) 11 Page - Fairchild Semiconductor |
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11 / 15 page  © 2011 Fairchild Semiconductor Corporation www.fairchildsemi.com FAN6754WA • Rev. 1.0.6 11 Functional Description Startup Current For startup, the HV pin is connected to the line input through an external diode and resistor; RHV, (1N4007 / 200 kΩ recommended). Peak startup current drawn from the HV pin is (VAC× 2 ) / RHV and charges the hold- up capacitor through the diode and resistor. When the VDD capacitor level reaches VDD-ON, the startup current switches off. At this moment, the VDD capacitor only supplies the FAN6754WA to keep the VDD until the auxiliary winding of the main transformer provides the operating current. Operating Current Operating current is around 1.5 mA. The low operating current enables better efficiency and reduces the requirement of VDD hold-up capacitance. Green-Mode Operation The proprietary Green-Mode function provides off-time modulation to reduce the switching frequency in light- load and no-load conditions. VFB, which is derived from the voltage feedback loop, is taken as the reference. Once VFB is lower than the threshold voltage (VFB-N), the switching frequency is continuously decreased to the minimum Green-Mode frequency of around 22 kHz. Current Sensing / PWM Current Limiting Peak-current-mode control is utilized to regulate output voltage and provide pulse-by-pulse current limiting. The switch current is detected by a sense resistor into the SENSE pin. The PWM duty cycle is determined by this current-sense signal and VFB, the feedback voltage. When the voltage on the SENSE pin reaches around VCOMP = (VFB–0.6)/4, the switch cycle is terminated immediately. VCOMP is internally clamped to a variable voltage around 0.46 V for low-line output power limit. Leading-Edge Blanking (LEB) Each time the power MOSFET is switched on, a turn-on spike occurs on the sense-resistor. To avoid premature termination of the switching pulse, a leading-edge blanking time is built in. During this blanking period, the current-limit comparator is disabled and cannot switch off the gate driver. Under-Voltage Lockout (UVLO) The turn-on and turn-off thresholds are fixed internally at 17V and 10V, respectively. During startup, the hold-up capacitor must be charged to 17 V through the startup resistor to enable the IC. The hold-up capacitor continues to supply VDD until the energy can be delivered from auxiliary winding of the main transformer. VDD must not drop below 10 V during startup. This UVLO hysteresis window ensures that hold-up capacitor is adequate to supply VDD during startup. Gate Output / Soft Driving The BiCMOS output stage is a fast totem-pole gate driver. Cross conduction has been avoided to minimize heat dissipation, increase efficiency, and enhance reliability. The output driver is clamped by an internal 13 V Zener diode to protect power MOSFET transistors against undesirable gate over voltage. A soft driving waveform is implemented to minimize EMI. Soft-Start For many applications, it is necessary to minimize the inrush current at startup. The built-in 8ms soft-start circuit significantly reduces the startup current spike and output voltage overshoot. Slope Compensation The sensed voltage across the current-sense resistor is used for peak-current-mode control and cycle-by-cycle current limiting. Built-in slope compensation improves stability and prevents sub-harmonic oscillation. FAN6754WA inserts a synchronized, positive-going, ramp at every switching cycle. Constant Output Power Limit When the SENSE voltage across sense resistor RSENSE reaches the threshold voltage, around 0.46 V for low- line condition, the output GATE drive is turned off after a small delay, tPD. This delay introduces an additional current proportional to tPD • VIN / LP. Since the delay is nearly constant, regardless of the input voltage VIN, higher input voltage results in larger additional power. Therefore, the maximum output power at high line is higher than that of low line. To compensate this variation for a wide AC input range, a power-limiter is controlled by the HV pin to solve the unequal power-limit problem. The power limiter is fed to the inverting input of the current limiting comparator. This results in a lower current limit at high-line inputs than at low-line inputs. Brownout and Constant Power Limited by the HV Pin Unlike previous PWM controllers, the FAN6754WA HV pin can detect the AC line voltage to perform brownout protection and line compensation for power limit. Using a fast diode and startup resistor to sample the AC line voltage, the peak value refreshes and is stored in a register at each sampling cycle. When internal update time is met, this peak value is used for brownout and current-limit level judgment. Equation (1) and (2) calculate the level of brown-in or brownout converted to RMS value. For power saving, FAN6754WA enlarges the sampling cycle to lower the power loss from HV sampling at light-load condition. 2 / ) 1.6 1.6) (R 0.9V ( (RMS) V HV ON - AC (1) 2 / ) 1.6 1.6) (R 0.81V ( (RMS) V HV OFF - AC (2) where RHV is in k. |
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