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AD9640ABCPZ-105 ๋ฐ์ดํ„ฐ์‹œํŠธ(HTML) 40 Page - Analog Devices

๋ถ€ํ’ˆ๋ช… AD9640ABCPZ-105
์ƒ์„ธ๋‚ด์šฉ  14-Bit, 80/105/125/150 MSPS, 1.8 V Dual Analog-to-Digital Converter
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AD9640ABCPZ-105 ๋ฐ์ดํ„ฐ์‹œํŠธ(HTML) 40 Page - Analog Devices

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AD9640
Rev. B | Page 40 of 52
SERIAL PORT INTERFACE (SPI)
The AD9640 serial port interface (SPI) allows the user to
configure the converter for specific functions or operations
through a structured register space provided inside the ADC.
This gives the user added flexibility and customization
depending on the application. Addresses are accessed via the
serial port and can be written to or read from via the port.
Memory is organized into bytes that can be further divided into
fields, which are documented in the Memory Map section. For
detailed operational information, see the AN-877 Application
Note, Interfacing to High Speed ADCs via SPI.
CONFIGURATION USING THE SPI
There are three pins that define the SPI of this ADC. They are
the SCLK/DFS pin, the SDIO/DCS pin, and the CSB pin (see
Table 22). The SCLK/DFS (a serial clock) is used to synchronize
the read and write data presented from and to the ADC. The
SDIO/DCS (serial data input/output) is a dual-purpose pin that
allows data to be sent and read from the internal ADC memory
map registers. The CSB (chip select bar) is an active-low control
that enables or disables the read and write cycles.
Table 22. Serial Port Interface Pins
Pin
Function
SCLK
Serial Clock. The serial shift clock input. SCLK is used to
synchronize serial interface reads and writes.
SDIO
Serial Data Input/Output. A dual-purpose pin. The typical
role for this pin is an input and output depending on the
instruction being sent and the relative position in the
timing frame.
CSB
Chip Select Bar. An active-low control that gates the read
and write cycles.
The falling edge of the CSB, in conjunction with the rising edge
of the SCLK, determines the start of the framing. An example of
the serial timing and its definitions can be found in Figure 73
and Table 8.
Other modes involving the CSB are available. The CSB can be
held low indefinitely, which permanently enables the device;
this is called streaming. The CSB may stall high between bytes
to allow for additional external timing. When CSB is tied high,
SPI functions are placed in high impedance mode. This mode
turns on any SPI pin secondary functions.
During an instruction phase, a 16-bit instruction is transmitted.
Data follows the instruction phase, and its length is determined
by the W0 and W1 bits. All data is composed of 8-bit words.
The first bit of the first byte in a multibyte serial data transfer frame
indicates whether a read command or a write command is
issued. This allows the serial data input/output (SDIO) pin to
change direction from an input to an output.
In addition to word length, the instruction phase determines if
the serial frame is a read or write operation, allowing the serial
port to be used to both program the chip as well as read the
contents of the on-chip memory. If the instruction is a readback
operation, performing a readback causes the serial data input/
output (SDIO) pin to change direction from an input to an output
at the appropriate point in the serial frame.
Data can be sent in MSB first mode or LSB first mode. MSB
first is the default on power-up and can be changed via the
configuration register. For more information about this and
other features, see the AN-877 Application Note, Interfacing to
High Speed ADCs via SPI.
HARDWARE INTERFACE
The pins described in Table 22 comprise the physical interface
between the userโ€™s programming device and the serial port of
the AD9640. The SCLK pin and the CSB pin function as inputs
when using the SPI interface. The SDIO pin is bidirectional,
functioning as an input during write phases and as an output
during readback.
The SPI interface is flexible enough to be controlled by either
FPGAs or microcontrollers. One method for SPI configuration
is described in detail in the AN-812 Application Note,
Microcontroller-Based Serial Port Interface Boot Circuit.
The SPI port should not be active during periods when the full
dynamic performance of the converter is required. Because the
SCLK signal, the CSB signal, and the SDIO signal are typically
asynchronous to the ADC clock, noise from these signals can
degrade converter performance. If the on-board SPI bus is utilized
for other devices, it may be necessary to provide buffers between
this bus and the AD9640 to keep these signals from transitioning
at the converter inputs during critical sampling periods.
Some pins serve a dual function when the SPI interface is not
being used. When the pins are strapped to AVDD or ground
during device power-on, they are associated with a specific
function. The Digital Outputs section describes the strappable
functions supported on the AD9640.


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