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AD9640ABCPZ-105 ๋ฐ์ดํ„ฐ์‹œํŠธ(HTML) 44 Page - Analog Devices

๋ถ€ํ’ˆ๋ช… AD9640ABCPZ-105
์ƒ์„ธ๋‚ด์šฉ  14-Bit, 80/105/125/150 MSPS, 1.8 V Dual Analog-to-Digital Converter
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ํ™ˆํŽ˜์ด์ง€  http://www.analog.com
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AD9640ABCPZ-105 ๋ฐ์ดํ„ฐ์‹œํŠธ(HTML) 44 Page - Analog Devices

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AD9640
Rev. B | Page 44 of 52
Addr
(Hex)
Register
Name
Bit 7
(MSB)
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
(LSB)
Default
Value
(Hex)
Default
Notes/
Comments
0x0E
BIST Enable
(Local)
Open
Open
Open
Open
Open
Reset BIST
sequence
Open
BIST enable
0x00
0x10
Offset Adjust
(Local)
Open
Open
Offset adjust in LSBs from +31 to โˆ’32
(twos complement format)
0x00
0x14
Output Mode
Drive
strength
0 V to 3.3 V
CMOS or
ANSI
LVDS:
1 V to 1.8 V
CMOS or
reduced:
LVDS
(global)
Output type
0 = CMOS
1 = LVDS
(global)
Open
Output
enable bar
(local)
Open
Output
invert
(local)
00 = offset binary
01 = twos complement
01 = gray code
11 = offset binary
(local)
0x00
Configures the
outputs and
the format of
the data
0x16
Clock Phase
Control
(Global)
Invert DCO
clock
Open
Open
Open
Open
Input clock divider phase adjust
000 = no delay
001 = 1 input clock cycle
010 = 2 input clock cycles
011 = 3 input clock cycles
100 = 4 input clock cycles
101 = 5 input clock cycles
110 = 6 input clock cycles
0x00
Allows
selection of
clock delays
into the input
clock divider
0x17
DCO Output
Delay (Global)
Open
Open
Open
DCO clock delay
(delay = 2500 ps ร— register value/31)
00000 = 0 ps
00001 = 81 ps
00010 = 161 ps
โ€ฆ
11110 = 2419 ps
11111 = 2500 ps
0x00
0x18
VREF Select
(Global)
Reference voltage selection
00 = 1.25 V p-p
01 = 1.5 V p-p
10 = 1.75 V p-p
11 = 2.0 V p-p (default)
Open
Open
Open
Open
Open
Open
0xC0
0x24
BIST Signature
LSB (Local)
BIST signature[7:0]
0x00
Read only
0x25
BIST Signature
MSB (Local)
BIST signature[15:8]
0x00
Read only
Digital Feature Control
0x100
Sync Control
(Global)
SM sync
enable
Open
Open
Open
Open
Clock
divider next
sync only
Clock
divider
sync
enable
Master
sync
enable
0x00
0x104
Fast Detect
Control (Local)
Open
Open
Open
Open
Fast Detect Mode Select[2:0]
Fast detect
enable
0x00
0x106
Fine Upper
Threshold
Register 0
(Local)
Fine Upper Threshold[7:0]
0x00
0x107
Fine Upper
Threshold
Register 1
(Local)
Open
Open
Open
Fine Upper Threshold[12:8]
0x00
0x108
Fine Lower
Threshold
Register 0
(Local)
Fine Lower Threshold[7:0]
0x00
0x109
Fine Lower
Threshold
Register 1
(Local)
Open
Open
Open
Fine Lower Threshold[12:8]
0x00


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