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AD9640ABCPZ-105 ๋ฐ์ดํ„ฐ์‹œํŠธ(HTML) 12 Page - Analog Devices

๋ถ€ํ’ˆ๋ช… AD9640ABCPZ-105
์ƒ์„ธ๋‚ด์šฉ  14-Bit, 80/105/125/150 MSPS, 1.8 V Dual Analog-to-Digital Converter
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AD9640ABCPZ-105 ๋ฐ์ดํ„ฐ์‹œํŠธ(HTML) 12 Page - Analog Devices

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AD9640
Rev. B | Page 12 of 52
TIMING SPECIFICATIONS
Table 8.
Parameter
Conditions
Min
Typ
Max
Unit
SYNC TIMING REQUIREMENTS
tSSYNC
SYNC to rising edge of CLK setup time
0.24
ns
tHSYNC
SYNC to rising edge of CLK hold time
0.40
ns
SPI TIMING REQUIREMENTS
tDS
Setup time between the data and the rising edge of SCLK
2
ns
tDH
Hold time between the data and the rising edge of SCLK
2
ns
tCLK
Period of the SCLK
40
ns
tS
Setup time between CSB and SCLK
2
ns
tH
Hold time between CSB and SCLK
2
ns
tHIGH
SCLK pulse width high
10
ns
tLOW
SCLK pulse width low
10
ns
tEN_SDIO
Time required for the SDIO pin to switch from an input to an
output relative to the SCLK falling edge
10
ns
tDIS_SDIO
Time required for the SDIO pin to switch from an output to
an input relative to the SCLK rising edge
10
ns
SPORT TIMING REQUIREMENTS
tCSSCLK
Delay from rising edge of CLK+ to rising edge of SMI SCLK
3.2
4.5
6.2
ns
tSSCLKSDO
Delay from rising edge of SMI SCLK to SMI SDO
โˆ’0.4
0
+0.4
ns
tSSCLKSDFS
Delay from rising edge of SMI SCLK to SMI SDFS
โˆ’0.4
0
+0.4
ns
Timing Diagrams
CLK+
DCOA/DCOB
CH A/B DATA
N
N+ 1
N+ 2
N+ 3
N+ 4
N+ 5
N+ 6
N+ 7
N+ 8
N โ€“ 12
N โ€“ 11
N โ€“ 9
N โ€“ 8
N โ€“ 7
N โ€“ 6
N โ€“ 5
N โ€“ 4
N โ€“ 13
CLKโ€“
tCLK
tPD
tS
tH
tDCO
tCLK
tA
CH A/B FAST
DETECT
N โ€“ 1
N + 2
N + 3
N + 4
N + 5
N + 6
N โ€“ 3
N โ€“ 2
N โ€“ 10
N + 1
N
Figure 2. CMOS Output Mode Data and Fast Detect Output Timing (Fast Detect Mode 0)


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