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AD9640ABCPZ-105 ๋ฐ์ดํ„ฐ์‹œํŠธ(HTML) 13 Page - Analog Devices

๋ถ€ํ’ˆ๋ช… AD9640ABCPZ-105
์ƒ์„ธ๋‚ด์šฉ  14-Bit, 80/105/125/150 MSPS, 1.8 V Dual Analog-to-Digital Converter
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AD9640ABCPZ-105 ๋ฐ์ดํ„ฐ์‹œํŠธ(HTML) 13 Page - Analog Devices

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AD9640
Rev. B | Page 13 of 52
CLK+
DCOโ€“
DCO+
CH A/CH B DATA
N
N + 1
N + 2
N + 3
N + 4
N + 5
N + 6
N + 7
N + 8
N โ€“ 12
N โ€“ 11
N โ€“ 9
N โ€“ 8
N โ€“ 7
N โ€“ 6
N โ€“ 5
N โ€“ 4
N โ€“ 13
CLKโ€“
tCLK
tPD
tCLK
tA
CH A/CH B FAST
DETECT
ABABAB
ABABAB
ABABA
A
B
N โ€“ 10
N โ€“ 6
N โ€“ 5
N โ€“ 3
N โ€“ 2
N โ€“ 1
N
N + 1
N + 2
N โ€“ 7
ABABAB
ABABAB
ABABA
A
B
N โ€“ 4
tDCO
Figure 3. LVDS Mode Data and Fast Detect Output Timing (Fast Detect Mode 1 Through Fast Detect Mode 5)
SYNC
CLK+
tHSYNC
tSSYNC
Figure 4. SYNC Input Timing Requirements
CLK+
SMI SCLK
SMI SDFS
DATA
DATA
SMI SDO
CLKโ€“
tCSSCLK
tSSCLKSDFS
tSSCLKSDO
Figure 5. Signal Monitor SPORT Output Timing (Divide by 2 Mode)


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