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ADC084S101 데이터시트(PDF) 7 Page - Texas Instruments |
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ADC084S101 데이터시트(HTML) 7 Page - Texas Instruments |
7 / 27 page tCSU tCLH SCLK CS SCLK tCONVERT tACQ tCL tACC tEN Z3 Z2 Z1 Z0 DB6 DONT DONTC ADD2 ADD1 ADD0 DONTC DONTC DONTC DB7 DB5 DB4 DB0 16 8 7 6 5 4 3 2 1 DIN DOUT SCLK CS tDIS Zero Zero DB1 15 14 13 Tri-State Zero Zero 12 11 tCH tH tSU ADC084S021 www.ti.com SNAS279E – APRIL 2005 – REVISED MARCH 2013 Figure 3. Timing Test Circuit Figure 4. ADC084S021 Serial Timing Diagram Figure 5. SCLK and CS Timing Parameters Specification Definitions ACQUISITION TIME is the time required to acquire the input voltage. That is, it is time required for the hold capacitor to charge up to the input voltage. APERTURE DELAY is the time between the fourth falling SCLK edge of a conversion and the time when the input signal is acquired or held for conversion. CONVERSION TIME is the time required, after the input voltage is acquired, for the ADC to convert the input voltage to a digital word. CROSSTALK is the coupling of energy from one channel into the other channel, or the amount of signal energy from one analog input that appears at the measured analog input. DIFFERENTIAL NON-LINEARITY (DNL) is the measure of the maximum deviation from the ideal step size of 1 LSB. DUTY CYCLE is the ratio of the time that a repetitive digital waveform is high to the total time of one period. The specification here refers to the SCLK. Copyright © 2005–2013, Texas Instruments Incorporated Submit Documentation Feedback 7 Product Folder Links: ADC084S021 |
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