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AD7801BRU 데이터시트(PDF) 8 Page - Analog Devices |
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AD7801BRU 데이터시트(HTML) 8 Page - Analog Devices |
8 / 16 page AD7801 –8– REV. 0 Reference The AD7801 has the ability to use either an external reference applied through the REFIN pin or an internal reference generated from VDD. Figure 20 shows the reference input arrangement where either the internal VDD/2 or the externally applied reference can be selected. The internal reference is selected by tying the REFIN pin to VDD. If an external reference is to be used, this can be directly applied to the REFIN pin and if this is 1 V below VDD, the internal circuitry will select this externally applied reference as the reference source for the DAC. Digital Interface The AD7801 contains a fast parallel interface allowing this DAC to interface to industry standard microprocessors, microcontrollers and DSP machines. There are two modes in which this parallel interface can be configured to update the DAC output. The synchronous update mode allows synchro- nous updating of the DAC output; the automatic update mode allows the DAC to be updated individually following a write cycle. Figure 21 shows the internal logic associated with the digital interface. The PON STRB signal is internally generated from the power-on reset circuitry and is low during the power- on reset phase of the power up procedure. CLEAR SET SLE LDAC ENABLE DAC CONTROL LOGIC MLE SLE CLR PON STRB CLR LDAC CS WR Figure 21. Logic Interface The AD7801 has a double buffered interface, which allows for synchronous updating of the DAC output. Figure 22 shows a block diagram of the register arrangement within the AD7801. MLE SLE CONTROL LOGIC CS WR LDAC CLR 4 15 15 30 8 4 15 15 30 LOWER NIBBLE UPPER NIBBLE DB7-DB0 Figure 22. Register Arrangement Automatic Update Mode In this mode of operation the LDAC signal is permanently tied low. The state of the LDAC is sampled on the rising edge of WR. LDAC being low allows the DAC register to be automati- cally updated on the rising edge of WR. The output update occurs on the rising edge of WR. Figure 23 shows the timing associated with the automatic update mode of operation and also the status of the various registers during this frame. HOLD HOLD TRACK TRACK D7-D0 WR CS LDAC = 0 I/P REG (MLE) DAC REG (SLE) VOUT TRACK HOLD Figure 23. Timing and Register Arrangement for Auto- matic Update Mode Synchronous Update Mode In this mode of operation the LDAC signal is used to update the DAC output to synchronize with other updates in the system. The state of the LDAC is sampled on the rising edge of WR. If LDAC is high, the automatic update mode is disabled and the DAC latch is updated at any time after the write by taking LDAC low. The output update occurs on the falling edge of LDAC. LDAC must be taken back high again before the next data transfer takes place. Figure 24 shows the timing associated with the synchronous update mode of operation and also the status of the various registers during this frame. HOLD HOLD D7-D0 WR CS LDAC I/P REG (MLE) DAC REG (SLE) VOUT HOLD HOLD TRACK TRACK Figure 24. Timing and Register Arrangement for Synchro- nous Update Mode |
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