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AD7888ARUZ 데이터시트(PDF) 4 Page - Analog Devices |
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AD7888ARUZ 데이터시트(HTML) 4 Page - Analog Devices |
4 / 17 page AD7888 –4– Limit at TMIN, TMAX (A, B Versions) Parameter 4.75 V to 5.25 V 2.7 V to 3.6 V Unit Description fSCLK 2 2 2 MHz max tCONVERT 14.5 tSCLK 14.5 tSCLK tACQ 1.5 tSCLK 1.5 tSCLK Throughput Time = tCONVERT + tACQ = 16 tSCLK t1 10 10 ns min CS to SCLK Setup Time t2 3 30 60 ns max Delay from CS until DOUT 3-State Disabled t3 3 75 100 ns max Data Access Time after SCLK Falling Edge t4 20 20 ns min Data Setup Time Prior to SCLK Rising Edge t5 20 20 ns min Data Valid to SCLK Hold Time t6 0.4 tSCLK 0.4 tSCLK ns min SCLK High Pulsewidth t7 0.4 tSCLK 0.4 tSCLK ns min SCLK Low Pulsewidth t8 4 80 80 ns max CS Rising Edge to DOUT High Impedance t9 55 µs typ Power-Up Time from Shutdown NOTES 1Sample tested at 25 °C to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of V DD) and timed from a voltage level of 1.6 V. 2Mark/Space ratio for the SCLK input is 40/60 to 60/40. See Serial Interface section. 3Measured with the load circuit of Figure 1 and defined as the time required for the output to cross 0.8 V or 2.4 V with V DD = 5 V ± 10% and time for an output to cross 0.4 V or 2.0 V with VDD = 3 V ± 10%. 4t 8 is derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 1. The measured number i s then extrapolated back to remove the effects of charging or discharging the 50 pF capacitor. This means that the time, t 8, quoted in the timing characteristics is the true bus relinquish time of the part and is independent of the bus loading. Specifications subject to change without notice. TIMING SPECIFICATIONS1 (T A = TMIN to TMAX, unless otherwise noted) 1.6V IOL 200 A 200 A IOH TO OUTPUT PIN CL 50pF Figure 1. Load Circuit for Digital Output Timing Specifications REV. C |
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