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ADM1066ASUZ 데이터시트(PDF) 4 Page - Analog Devices

부품명 ADM1066ASUZ
상세설명  Super Sequencer with Margining Control and Auxiliary ADC Inputs
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홈페이지  http://www.analog.com
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ADM1066
Rev. E | Page 4 of 32
The device also provides up to 10 programmable inputs for moni-
toring undervoltage faults, overvoltage faults, or out-of-window
faults on up to 10 supplies. In addition, 10 programmable outputs
can be used as logic enables. Six of these programmable outputs
can also provide up to a 12 V output for driving the gate of an N-
FET that can be placed in the path of a supply.
The logical core of the device is a sequencing engine. This state
machine-based construction provides up to 63 different states.
This design enables very flexible sequencing of the outputs,
based on the condition of the inputs.
The device is controlled via configuration data that can be
programmed into an EEPROM. The entire configuration can
be programmed using an intuitive GUI-based software package
provided by Analog Devices, Inc.
DETAILED BLOCK DIAGRAM
GPI SIGNAL
CONDITIONING
SFD
GPI SIGNAL
CONDITIONING
SFD
SFD
SFD
SELECTABLE
ATTENUATOR
SELECTABLE
ATTENUATOR
DEVICE
CONTROLLER
OSC
EEPROM
SDA SCL A1
A0
SMBus
INTERFACE
REFOUT
REFIN
AUX1
AUX2
REFGND
VREF
12-BIT
SAR ADC
ADM1066
CONFIGURABLE
OUTPUT DRIVER
(HV)
PDO1
PDO2
PDOGND
PDO3
DAC1
VOUT
DAC
DAC6
VOUT
DAC
VCCP
GND
DAC2 DAC3 DAC4 DAC5
PDO4
PDO5
PDO8
PDO9
CONFIGURABLE
OUTPUT DRIVER
(HV)
PDO6
CONFIGURABLE
OUTPUT DRIVER
(LV)
PDO7
CONFIGURABLE
OUTPUT DRIVER
(LV)
PDO10
SEQUENCING
ENGINE
VX2
VX3
VX4
VP2
VP3
VP4
VH
VP1
VX1
AGND
VX5
VDDCAP
VDD
ARBITRATOR
REG 5.25V
CHARGE PUMP
Figure 2. Detailed Block Diagram


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