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ADV7127JR240 데이터시트(PDF) 7 Page - Analog Devices |
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ADV7127JR240 데이터시트(HTML) 7 Page - Analog Devices |
7 / 16 page ADV7127 –7– REV. 0 3.3 V TIMING SPECIFICATIONS1 Parameter Min Typ Max Units Condition ANALOG OUTPUTS Analog Output Delay, t6 7.5 ns Analog Output Rise/Fall Time, t7 4 1.0 ns Analog Output Transition Time, t8 5 15 ns Analog Output Skew, t9 6 12 ns CLOCK CONTROL fCLK 7 50 MHz 50 MHz Grade fCLK 7 140 MHz 140 MHz Grade fCLK 7 240 MHz 240 MHz Grade Data and Control Setup, t2 6 1.5 ns Data and Control Hold, t2 6 2.5 ns Clock Pulsewidth High, t4 1.1 ns fMAX = 240 MHz Clock Pulsewidth Low t5 6 1.4 ns fMAX = 240 MHz Clock Pulsewidth High t4 6 2.85 ns fMAX = 140 MHz Clock Pulsewidth Low t5 6 2.85 ns fMAX = 140 MHz Clock Pulsewidth High t4 6 8.0 ns fMAX = 50 MHz Clock Pulsewidth Low t5 6 8.0 ns fMAX = 50 MHz Pipeline Delay, tPD 6 1.0 1.0 1.0 Clock Cycles PSAVE Up Time, t10 6 410 ns PDOWN Up Time, t11 8 320 ns NOTES 1Timing specifications are measured with input levels of 3.0 V (V IH) and 0 V (VIL) 0 for both 5 V and 3.3 V supplies. 2These maximum and minimum specifications are guaranteed over this range. 3Temperature range: T MIN to TMAX: –40°C to +85 °C at 50 MHz and 140 MHz, 0 °C to +70°C at 240 MHz. 4Rise time was measured from the 10% to 90% point of zero to full-scale transition, fall time from the 90% to 10% point of a full-scale transition. 5Measured from 50% point of full-scale transition to 2% of final value. 6Guaranteed by characterization. 7f CLK max specification production tested at 125 MHz and 5 V limits specified here are guaranteed by characterization. 8This power-down feature is only available on the ADV7127 in the TSSOP package. Specifications subject to change without notice. CLOCK DATA t4 t5 t7 t8 NOTES: 1. OUTPUT DELAY ( t6) MEASURED FROM THE 50% POINT OF THE RISING EDGE OF CLOCK TO THE 50% POINT OF FULL SCALE TRANSITION. 2. OUTPUT RISE/FALL TIME ( t7) MEASURED BETWEEN THE 10% AND 90% POINTS OF FULL SCALE TRANSITION. 3. TRANSITION TIME ( t8) MEASURED FROM THE 50% POINT OF FULL SCALE TRANSITION TO WITHIN 2% OF THE FINAL OUTPUT VALUE. t2 ANALOG OUTPUTS (IOUT, ) DIGITAL INPUTS (D9–D0) t3 t1 t6 IOUT Figure 1. Timing Diagram (VAA = +3.0 V–3.6 V 2, V REF = 1.235 V, RSET = 560 . All specifications TMIN to TMAX 3 unless otherwise noted, TJ MAX = 110 C) |
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