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AD7450ABRM-REEL7 데이터시트(PDF) 4 Page - Analog Devices

부품명 AD7450ABRM-REEL7
상세설명  Differential Input, 1 MSPS ADCs in an 8-Lead SOT-23
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AD7440/AD7450A
Rev. C | Page 4 of 28
Parameter
Test Conditions/Comments
B Version
Unit
CONVERSION RATE
Conversion Time
888 ns with an 18 MHz SCLK
16
SCLK cycles
Track-and-Hold Acquisition Time2
Sine wave input
200
ns max
Step input
290
ns max
Throughput Rate
1
MSPS max
POWER REQUIREMENTS
VDD
Range: 3 V + 20%/–10%; 5 V ± 5%
2.7/5.25
V min/V max
IDD8
Normal Mode (Static)
SCLK on or off
0.5
mA typ
Normal Mode (Operational)
VDD = 4.75 V to 5.25 V
1.95
mA max
VDD = 2.7 V to 3.6 V
1.45
mA max
Full Power-Down Mode
SCLK on or off
1
μA max
Power Dissipation
Normal Mode (Operational)
VDD = 5 V, 1.55 mW typ for 100 kSPS9
9.25
mW max
VDD = 3 V, 0.6 mW typ for 100 kSPS9
4
mW max
Full Power-Down Mode
VDD = 5 V, SCLK on or off
5
μW max
VDD = 3 V, SCLK on or off
3
μW max
1 Common-mode voltage. The input signal can be centered on a dc common-mode voltage in the range specified in Figure 28 and Figure 29.
2 See the Terminology section.
3 Analog inputs with slew rates exceeding 27 V/μs (full-scale input sine wave > 3.5 MHz) within the acquisition time can cause the converter to return an
incorrect result.
4 Because the input spans of VIN+ and VIN– are both VREF and are 180° out of phase, the differential voltage is 2 × VREF.
5 The AD7440 is functional with a reference input from 100 mV and for VDD = 5 V; the reference can range up to 3.5 V.
6 The AD7440 is functional with a reference input from 100 mV and for VDD = 3 V; the reference can range up to 2.2 V.
7 Guaranteed by characterization.
8 Measured with a midscale dc input.
9 See the Power vs. Throughput section.


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