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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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SN74GTLP1395PWRG4 데이터시트(PDF) 9 Page - Texas Instruments |
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SN74GTLP1395PWRG4 데이터시트(HTML) 9 Page - Texas Instruments |
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9 / 24 page  www.ti.com Skew Characteristics(1) SN74GTLP1395 TWO 1-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE BUS TRANSCEIVERS WITH SPLIT LVTTL PORT, FEEDBACK PATH, AND SELECTABLE POLARITY SCES349C–JUNE 2001–REVISED JANUARY 2006 over recommended ranges of supply voltage and operating free-air temperature, VREF =1V, standard lumped loads (CL = 30 pF for B port and CL = 50 pF for Y port) (unless otherwise noted) (see Figure 1) FROM TO PARAMETER EDGE RATE(2) MIN MAX UNIT (INPUT) (OUTPUT) tsk(LH)(3) 0.3 A B Slow ns tsk(HL)(3) 0.4 tsk(LH)(3) 0.3 AB Fast ns tsk(HL)(3) 0.3 tsk(LH)(3) 0.4 BY ns tsk(HL)(3) 0.2 Slow 1.8 AB tsk(t)(3) Fast 1.5 ns BY 1 tsk(prLH)(4) 0.7 A B Slow ns tsk(prHL)(4) 2 tsk(prLH)(4) 0.5 AB Fast ns tsk(prHL)(4) 1.7 tsk(prLH)(4) 1.2 BY ns tsk(prHL)(4) 1.6 (1) Actual skew values between GTLP outputs could vary on the backplane due to the loading and impedance seen by the device. (2) Slow (ERC = L) and Fast (ERC = H) (3) tsk(LH)/tsk(HL) and tsk(t) – Output-to-output skew is defined as the absolute value of the difference between the actual propagation delay for all outputs with the same packaged device. The specifications are given for specific worst-case VCC and temperature and apply to any outputs switching in the same direction either high to low [tsk(HL)] or low to high [tsk(LH)] or in opposite directions, both low to high and high to low [tsk(t)]. (4) tsk(prLH)/tsk(prHL) – The magnitude of the difference in propagation delay times between corresponding terminals of two logic devices when both logic devices operate with the same supply voltages and at the same temperature, and have identical package types, identical specified loads, and identical logic functions. Furthermore, these values are provided by SPICE simulations. 9 |
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