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SN74GTLP1395DWR 데이터시트(PDF) 11 Page - Texas Instruments

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부품명 SN74GTLP1395DWR
상세설명  TWO 1-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE BUS TRANSCEIVERS
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DISTRIBUTED-LOAD BACKPLANE SWITCHING CHARACTERISTICS
From Output
Under Test
Test
Point
1.5 V
CL = 18 pF
11 Ω
LL = 14 nH
Drvr
1.5 V
0.25”
1”
1”
1”
1.5 V
1”
1”
1”
0.25”
Rcvr
Rcvr
Rcvr
Slot 1
Slot 2
Slot 19
Slot 20
Conn.
Conn.
Conn.
Conn.
ZO = 50 Ω
Switching Characteristics
SN74GTLP1395
TWO 1-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE BUS TRANSCEIVERS
WITH SPLIT LVTTL PORT, FEEDBACK PATH, AND SELECTABLE POLARITY
SCES349C–JUNE 2001–REVISED JANUARY 2006
The preceding switching characteristics table shows the switching characteristics of the device into a lumped
load (Figure 1). However, the designer's backplane application probably is a distributed load. The physical
representation is shown in Figure 2. This backplane, or distributed load, can be approximated closely to a
resistor inductance capacitance (RLC) circuit, as shown in Figure 3. This device has been designed for optimum
performance in this RLC circuit. The following switching characteristics table shows the switching characteristics
of the device into the RLC load, to help the designer better understand the performance of the GTLP device in
the backplane. See www.ti.com/sc/gtlp for more information.
Figure 2. High-Drive Test Backplane
Figure 3. High-Drive RLC Network
over recommended operating conditions for the bus transceiver function (unless otherwise noted) (see Figure 3)
FROM
TO
PARAMETER
EDGE RATE(1)
TYP(2) UNIT
(INPUT)
(OUTPUT)
tPLH
4.3
AB
Slow
ns
tPHL
4.2
tPLH
3.8
AB
Fast
ns
tPHL
3.4
tPLH
6.1
AY
Slow
ns
tPHL
5.9
tPLH
5.6
AY
Fast
ns
tPHL
5.4
Slow
1.5
tr
Rise time, B outputs (20% to 80%)
ns
Fast
1
Slow
2.6
tf
Fall time, B outputs (80% to 20%)
ns
Fast
2
(1) Slow (ERC = H) and Fast (ERC = L)
(2) All typical values are at VCC = 3.3 V, TA =25°C. All values are derived from TI SPICE models.
11


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