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AD5323ARU-REEL7 데이터시트(PDF) 9 Page - Analog Devices |
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AD5323ARU-REEL7 데이터시트(HTML) 9 Page - Analog Devices |
9 / 28 page AD5303/AD5313/AD5323 Rev. B | Page 9 of 28 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 1 2 3 4 5 6 7 8 LDAC VDD VREFB BUF A VOUTA VREFA CLR BUF B 16 15 14 13 12 11 10 9 GND DIN SCLK PD DCEN VOUTB SYNC SDO AD5303/ AD5313/ AD5323 TOP VIEW (Not to Scale) Figure 6. Pin Configuration Table 5. Pin Function Descriptions Pin No. Mnemonic Description 1 CLR Active Low Control Input. Loads all zeros to both input and DAC registers. 2 LDAC Active Low Control Input. Transfers the contents of the input registers to their respective DAC registers. Pulsing this pin low allows either or both DAC registers to be updated if the input registers have new data. This allows the simultaneous update of both DAC outputs. 3 VDD Power Supply Input. These parts can be operated from 2.5 V to 5.5 V, and the supply should be decoupled to GND. 4 VREFB Reference Input Pin for DAC B. It may be configured as a buffered or an unbuffered input, depending on the state of the BUF B pin. It has an input range from 0 V to VDD in unbuffered mode and from 1 V to VDD in buffered mode. 5 VREFA Reference Input Pin for DAC A. It may be configured as a buffered or an unbuffered input depending on the state of the BUF A pin. It has an input range from 0 to VDD in unbuffered mode and from 1 V to VDD in buffered mode. 6 VOUTA Buffered Analog Output Voltage from DAC A. The output amplifier has rail-to-rail operation. 7 BUF A Control Pin. Controls whether the reference input for DAC A is unbuffered or buffered. If this pin is tied low, the reference input is unbuffered. If it is tied high, the reference input is buffered. 8 BUF B Control Pin. Controls whether the reference input for DAC B is unbuffered or buffered. If this pin is tied low, the reference input is unbuffered. If it is tied high, the reference input is buffered. 9 DCEN This pin is used to enable the daisy-chaining option. This should be tied high if the part is being used in a daisy chain. The pin should be tied low if it is being used in standalone mode. 10 PD Active Low Control Input. Acts as a hardware power-down option. This pin overrides any software power-down option. Both DACs go into power-down mode when this pin is tied low. The DAC outputs go into a high impedance state and the current consumption of the part drops to 200 nA @ 5 V (50 nA @ 3 V). 11 VOUTB Buffered Analog Output Voltage from DAC B. The output amplifier has rail-to-rail operation. 12 SYNC Active Low Control Input. This is the frame synchronization signal for the input data. When SYNC goes low, it powers on the SCLK and DIN buffers and enables the input shift register. Data is transferred in on the falling edges of the following 16 clocks. If SYNC is taken high before the 16th falling edge, the rising edge of SYNC acts as an interrupt and the write sequence is ignored by the device. 13 SCLK Serial Clock Input. Data is clocked into the input shift register on the falling edge of the serial clock input. Data can be transferred at rates up to 30 MHz. The SCLK input buffer is powered down after each write cycle. 14 DIN Serial Data Input. This device has a 16-bit shift register. Data is clocked into the register on the falling edge of the serial clock input. The DIN input buffer is powered down after each write cycle. 15 GND Ground Reference Point for All Circuitry on the Part. 16 SDO Serial Data Output. Can be used for daisy-chaining a number of these devices together or for reading back the data in the shift register for diagnostic purposes. The serial data output is valid on the falling edge of the clock. |
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