전자부품 데이터시트 검색엔진 |
|
AD9243ASZ 데이터시트(PDF) 9 Page - Analog Devices |
|
AD9243ASZ 데이터시트(HTML) 9 Page - Analog Devices |
9 / 24 page AD9243 REV. A –9– The input SHA of the AD9243 is optimized to meet the perfor- mance requirements for some of the most demanding commu- nication, imaging, and data acquisition applications while maintaining low power dissipation. Figure 22 is a graph of the full-power bandwidth of the AD9243, typically 40 MHz. Note that the small signal bandwidth is the same as the full-power bandwidth. The settling time response to a full-scale stepped input is shown in Figure 23 and is typically 80 ns to 0.0025%. The low input referred noise of 0.36 LSB’s rms is displayed via a grounded histogram and is shown in Figure 13. FREQUENCY – MHz 0 –3 –12 1 100 10 –6 –9 Figure 22. Full-Power Bandwidth SETTLING TIME – ns 16000 12000 0 060 10 20 30 40 50 8000 4000 70 80 Figure 23. Settling Time The SHA’s optimum distortion performance for a differential or single-ended input is achieved under the following two condi- tions: (1) the common-mode voltage is centered around mid supply (i.e., AVDD/2 or approximately 2.5 V) and (2) the input signal voltage span of the SHA is set at its lowest (i.e., 2 V input span). This is due to the sampling switches, QS1, being CMOS switches whose RON resistance is very low but has some signal dependency which causes frequency dependent ac distortion while the SHA is in the track mode. The RON resistance of a CMOS switch is typically lowest at its midsupply but increases symmetrically as the input signal approaches either AVDD or AVSS. A lower input signal voltage span centered at midsupply reduces the degree of RON modulation. Figure 24 compares the AD9243’s THD vs. frequency perfor- mance for a 2 V input span with a common-mode voltage of 1 V and 2.5 V. Note the difference in the amount of degrada- tion in THD performance as the input frequency increases. Similarly, note how the THD performance at lower frequencies becomes less sensitive to the common-mode voltage. As the input frequency approaches dc, the distortion will be domi- nated by static nonlinearities such as INL and DNL. It is important to note that these dc static nonlinearities are inde- pendent of any RON modulation. FREQUENCY – MHz –50 –60 –90 0.1 1 10 –70 –80 VCM = 1.0V VCM = 2.5V Figure 24. AD9243 THD vs. Frequency for VCM = 2.5 V and 1.0 V (AIN = –0.5 dB, Input Span = 2.0 V p-p) Due to the high degree of symmetry within the SHA topology, a significant improvement in distortion performance for differen- tial input signals with frequencies up to and beyond Nyquist can be realized. This inherent symmetry provides excellent cancella- tion of both common-mode distortion and noise. Also, the required input signal voltage span is reduced by a half which further reduces the degree of RON modulation and its effects on distortion. The optimum noise and dc linearity performance for either differential or single-ended inputs is achieved with the largest input signal voltage span (i.e., 5 V input span) and matched input impedance for VINA and VINB. Note that only a slight degradation in dc linearity performance exists between the 2 V and 5 V input span as specified in the AD9243 “DC SPECIFICATIONS.” Referring to Figure 21, the differential SHA is implemented using a switched-capacitor topology. Hence, its input imped- ance and its subsequent effects on the input drive source should be understood to maximize the converter’s performance. The combination of the pin capacitance, CPIN, parasitic capacitance CPAR, and the sampling capacitance, CS, is typically less than 16 pF. When the SHA goes into track mode, the input source must charge or discharge the voltage stored on CS to the new input voltage. This action of charging and discharging CS which is approximately 4 pF, averaged over a period of time and for a given sampling frequency, FS, makes the input impedance ap- pear to have a benign resistive component (i.e., 83 k Ω at F S = 3.0 MSPS). However, if this action is analyzed within a sam- pling period (i.e., T = <1/FS), the input impedance is dynamic due to the instantaneous requirement of charging and discharg- ing CS. A series resistor inserted between the input drive source and the SHA input as shown in Figure 25 provides the effective isolation. |
유사한 부품 번호 - AD9243ASZ |
|
유사한 설명 - AD9243ASZ |
|
|
링크 URL |
개인정보취급방침 |
ALLDATASHEET.CO.KR |
ALLDATASHEET 가 귀하에 도움이 되셨나요? [ DONATE ] |
Alldatasheet는? | 광고문의 | 운영자에게 연락하기 | 개인정보취급방침 | 링크교환 | 제조사별 검색 All Rights Reserved©Alldatasheet.com |
Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
Family Site : ic2ic.com |
icmetro.com |