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74AUP1G3208GW 데이터시트(PDF) 1 Page - NXP Semiconductors

부품명 74AUP1G3208GW
상세설명  Low-power 3-input OR-AND gate
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제조업체  NXP [NXP Semiconductors]
홈페이지  http://www.nxp.com
Logo NXP - NXP Semiconductors

74AUP1G3208GW 데이터시트(HTML) 1 Page - NXP Semiconductors

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1.
General description
The 74AUP1G3208 provides the Boolean function: Y = (A + B)
× C. The user can choose
the logic functions OR, AND and OR-AND. All inputs can be connected to VCC or GND.
Schmitt trigger action at all inputs makes the circuit tolerant to slower input rise and fall
times across the entire VCC range from 0.8 V to 3.6 V.
This device ensures a very low static and dynamic power consumption across the entire
VCC range from 0.8 V to 3.6 V.
This device is fully specified for partial power-down applications using IOFF.
The IOFF circuitry disables the output, preventing the damaging backflow current through
the device when it is powered down.
2.
Features and benefits
Wide supply voltage range from 0.8 V to 3.6 V
High noise immunity
Complies with JEDEC standards:
JESD8-12 (0.8 V to 1.3 V)
JESD8-11 (0.9 V to 1.65 V)
JESD8-7 (1.2 V to 1.95 V)
JESD8-5 (1.8 V to 2.7 V)
JESD8-B (2.7 V to 3.6 V)
ESD protection:
HBM JESD22-A114F Class 3A exceeds 5000 V
MM JESD22-A115-A exceeds 200 V
CDM JESD22-C101E exceeds 1000 V
Low static power consumption; ICC = 0.9
μA (maximum)
Latch-up performance exceeds 100 mA per JESD 78 Class II
Inputs accept voltages up to 3.6 V
Low noise overshoot and undershoot < 10 % of VCC
IOFF circuitry provides partial Power-down mode operation
Multiple package options
Specified from
−40 °Cto+85 °C and −40 °Cto+125 °C
74AUP1G3208
Low-power 3-input OR-AND gate
Rev. 5 — 22 June 2012
Product data sheet


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