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74ACT373SC 데이터시트(PDF) 2 Page - Fairchild Semiconductor |
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74ACT373SC 데이터시트(HTML) 2 Page - Fairchild Semiconductor |
2 / 14 page ©1988 Fairchild Semiconductor Corporation www.fairchildsemi.com 74AC373, 74ACT373 Rev. 1.5.0 2 Connection Diagram Pin Description Functional Description The AC/ACT373 contains eight D-type latches with 3-STATE standard outputs. When the Latch Enable (LE) input is HIGH, data on the Dn inputs enters the latches. In this condition the latches are transparent, i.e., a latch output will change state each time its D-type input changes. When LE is LOW, the latches store the infor- mation that was present on the D-type inputs a setup time preceding the HIGH-to-LOW transition of LE. The 3-STATE standard outputs are controlled by the Output Enable (OE) input. When OE is LOW, the standard outputs are in the 2-state mode. When OE is HIGH, the standard outputs are in the high impedance mode but this does not interfere with entering new data into the latches. Logic Symbols IEEE/IEC Truth Table H = HIGH Voltage Level L = LOW Voltage Level Z = High Impedance X = Immaterial O0 = Previous O0 before HIGH-to-LOW transition of Latch Enable Pin Names Description D0–D7 Data Inputs LE Latch Enable Input OE Output Enable Input O0–O7 3-STATE Latch Outputs Inputs Outputs LE OE Dn On XHX Z HL L L HLH H LL X O0 |
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