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ADV7281WBCPZ-M 데이터시트(PDF) 9 Page - Analog Devices |
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ADV7281WBCPZ-M 데이터시트(HTML) 9 Page - Analog Devices |
9 / 32 page Data Sheet ADV7281 Rev. A | Page 9 of 32 PIXEL PORT TIMING SPECIFICATIONS (ADV7281 ONLY) AVDD, DVDD, and PVDD = 1.71 V to 1.89 V, DVDDIO = 1.62 V to 3.63 V, specified at operating temperature range, unless otherwise noted. Specifications guaranteed by characterization. Table 6. Parameter Symbol Test Conditions/Comments Min Typ Max Unit CLOCK OUTPUTS LLC Mark Space Ratio t16:t17 45:55 55:45 % duty cycle DATA AND CONTROL OUTPUTS Data Output Transitional Time t18 Negative clock edge to start of valid data (tSETUP = t17 − t18) 3.8 ns t19 End of valid data to negative clock edge (tHOLD = t16 − t19) 6.9 ns OUTPUT LLC OUTPUTS P0 TO P7 t16 t17 t18 t19 Figure 6. ADV7281 Pixel Port and Control Output Timing Diagram |
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