AD7686

Rev. B | Page 7 of 28

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

VIO

10

SDI

9

SCK

8

SDO

7

CNV

6

AD7686

TOP VIEW

(Not to Scale)

Figure 5. 10-Lead MSOP Pin Configuration

1

REF

2

VDD

3

IN+

4

IN–

5

GND

10 VIO

9SDI

8SCK

7SDO

6CNV

TOP VIEW

(Not to Scale)

AD7686

Figure 6. 10-Lead QFN (LFCSP) Pin Configuration

Table 6. Pin Function Descriptions

Pin No.

Mnemonic

Type1

Description

1

REF

AI

Reference Input Voltage. The REF range is from 0.5 V to VDD. It is referred to the GND pin. This pin should

be decoupled closely to the pin with a 10 μF capacitor.

2

VDD

P

Power Supply.

3

IN+

AI

4

IN−

AI

Analog Input Ground Sense. It is connected to the analog ground plane or to a remote sense ground.

5

GND

P

Power Supply Ground.

6

CNV

DI

Convert Input. This input has multiple functions. On its leading edge, it initiates the conversions and

selects the interface mode, chain, or CS. In CS mode, it enables the SDO pin when low. In chain mode,

the data should be read when CNV is high.

7

SDO

DO

Serial Data Output. The conversion result is output on this pin. It is synchronized to SCK.

8

SCK

DI

Serial Data Clock Input. When the part is selected, the conversion result is shifted out by this clock.

9

SDI

DI

Serial Data Input. This input provides multiple features. It selects the interface mode of the ADC as

follows:

Chain mode is selected if SDI is low during the CNV rising edge. In this mode, SDI is used as a data

input to daisy-chain the conversion results of two or more ADCs onto a single SDO line. The digital

data level on SDI is output on SDO with a delay of 16 SCK cycles.

CS mode is selected if SDI is high during the CNV rising edge. In this mode, either SDI or CNV can

enable the serial output signals when low. If SDI or CNV is low when the conversion is completed,

the busy indicator feature is enabled.

10

VIO

P

Input/Output Interface Digital Power. Nominally at the same supply as the host interface (1.8 V, 2.5 V,

3 V, or 5 V).