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ADF4001BRU 데이터시트(PDF) 8 Page - Analog Devices |
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ADF4001BRU 데이터시트(HTML) 8 Page - Analog Devices |
8 / 28 page AD8348 Rev. A | Page 8 of 28 Pin No. Mnemonic Description Equivalent Circuit 15 ENBL Chip Enable Input. Active high. Threshold is equal to VS/2. D 17 VGIN Gain Control Input. The voltage on this pin controls the gain on the IF VGA. The gain control voltage range is from 0.2 V to 1.2 V and corresponds to a conversion gain range from +25.5 dB to −18.5 dB. This is the gain to the output of the mixers (that is, IMXO and QMXO). There is an additional 20 dB of fixed gain in the final baseband amplifiers (IAIN to IOPP/IOPN and QAIN to QOPP/QOPN). Note that the gain control function has a negative sense (that is, increasing voltage decreases gain). D 18, 19 MXIP, MXIN Auxiliary Mixer Inputs. If ENVG is low, the IFIP and IFIN inputs are disabled and MXIP and MXIN are enabled, allowing the VGA to be bypassed. The auxiliary mixer inputs are fully differential inputs that should be ac-coupled to the signal source. I 24 ENVG Active High VGA Enable. When ENVG is high, IFIP and IFIN inputs are enabled and MXIP and MXIN inputs are disabled. When ENVG is low, MXIP and MXIN inputs are enabled and IFIP and IFIN inputs are disabled. D 27 COM1 LO Section Ground. |
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