AD8370

Data Sheet

Rev. B | Page 6 of 28

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

6

7

8

11

10

9

AD8370

TOP VIEW

(Not to Scale)

2

3

4

5

15

14

1

16

13

12

INHI

ICOM

VCCI

PWUP

VOCM

VCCO

OCOM

OPHI

OPLO

OCOM

VCCO

LTCH

CLCK

DATA

ICOM

INLO

Figure 3.16-Lead TSSOP

Table 3. Pin Function Descriptions

Pin No.

Mnemonic

Description

1

INHI

Balanced Differential Input. Internally biased.

2, 15, PADDLE

ICOM

Input Common. Connect to a low impedance ground. This node is also connected to the exposed pad

on the bottom of the device.

3

VCCI

Input Positive Supply. 3.0 V to 5.5 V. Should be properly bypassed.

4

PWUP

Power Enable Pin. Device is operational when PWUP is pulled high.

5

VOCM

to this pin for external bypassing for additional common-mode supply decoupling. This can be achieved

with a bypass capacitor to ground. This pin is an output only and is not to be driven externally.

6, 11

VCCO

Output Positive Supply. 3.0 V to 5.5 V. Should be properly bypassed.

7, 10

OCOM

Output Common. Connect to a low impedance ground.

8

OPHI

Balanced Differential Output. Biased to midsupply.

9

OPLO

Balanced Differential Output. Biased to midsupply.

12

LTCH

Serial Data Latch Pin. Serial data is clocked into the shift register via the DATA pin when LTCH is low. Data

in shift register is latched on the next high-going edge.

13

CLCK

Serial Clock Input Pin.

14

DATA

Serial Data Input Pin.

16

INLO

Balanced Differential Input. Internally biased.