LC72131K, LC72131KMA

No.A0788-9/22

Control Data Functions

No.

Control block/data

Functions

Related data

(1)

Programmable

divider data

P0 to P15

DVS, SNS

Data that sets the divisor of the programmable divider.

A binary value in which P15 is the MSB. The LSB changes depending on

DVS and SNS. (*: don’t care)

Note: P0 to P3 are ignored when P4 is the LSB.

Selects the signal input pin (AMIN or FMIN) for the programmable divider, switches

the input frequency range. (*: don’t care)

Note: See the “Programmable Divider Structure” item for more information.

(2)

Reference divider

data

R0 to R3

XS

Reference frequency (fref) selection data.

Note *: PLL INHIBIT

The programmable divider block and the IF counter block are stopped, the FMIN, AMIN,

and IFIN pins are set to the pull-down state (ground), and the charge pump goes to the

high impedance state.

Crystal resonator selection

XS=0: 4.5MHz

XS=1: 7.2MHz

The 7.2MHz frequency is selected after the power-on reset.

(3)

IF counter control

data

CTE

GT0, GT1

IF counter measurement start data

CTE=1: Counter start

=0: Counter reset

Determines the IF counter measurement period.

Note: See the “IF Counter Structure” item for more information.

IFS

Continued on next page.

Twice the value of the setting

The value of the setting

The value of the setting

272 to 65535

272 to 65535

4 to 4095

Actual divisor

Divisor setting (N)

LSB

SNS

P0

P0

P4

*

1

0

1

0

0

DVS

10 to 160MHz

2 to 40MHz

0.5 to 10MHz

FMIN

AMIN

AMIN

Input frequency range

Input pin

SNS

*

1

0

1

0

0

DVS

1

* PLL INHIBIT

* PLL INHIBIT + X'tal OSC STOP

1

0

1

1

1

1

1

0

1

0

0

1

1

1

1

3

15

10

9

5

1

0

1

0

1

0

0

1

1

0

0

0

0

1

1

1

1

100kHz

50

25

25

12.5

6.25

3.125

3.125

0

1

0

1

0

1

0

1

0

0

1

1

0

0

1

1

0

0

0

0

1

1

1

1

0

0

0

0

0

0

0

0

Reference frequency

R0

R1

R2

R3

Wait time (ms)

Measurement time (ms)

GT0

GT1

3 to 4

3 to 4

7 to 8

7 to 8

4

8

32

64

0

1

0

1

0

0

1

1