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ADE7978 데이터시트(PDF) 9 Page - Analog Devices

부품명 ADE7978
상세설명  Isolated Energy Metering Chipset for Polyphase Shunt Meters
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Data Sheet
ADE7978/ADE7933/ADE7932
Rev. 0 | Page 9 of 120
ADE7978 SPECIFICATIONS
VDD = 3.3 V ± 10%, GND = DGND = 0 V, XTALIN = 16.384 MHz, TMIN to TMAX = −40°C to +85°C, TTYP = 25°C.
Table 2.
Parameter1, 2
Min
Typ
Max
Unit
Test Conditions/Comments
CLOCK INPUT
All specifications for CLKIN = 16.384 MHz
Input Clock Frequency, CLKIN
16.22
16.384
16.55
MHz
Minimum = 16.384 MHz − 1%; maximum
= 16.384 MHz + 1%
XTALIN Logic Inputs
Input High Voltage, VINH
2.4
V
Input Low Voltage, VINL
0.8
V
XTALIN Total Capacitance3
40
pF
XTALOUT Total Capacitance3
40
pF
CLOCK OUTPUT
Output Clock Frequency at CLKOUT Pin
4.096
MHz
Duty Cycle
50
%
Output High Voltage, VOH
2.4
V
ISOURCE
4.8
mA
Output Low Voltage, VOL
0.4
V
ISINK
4.8
mA
LOGIC INPUTS—MOSI/SDA, SCLK/SCL,
SS/HSA, DATA_A, DATA_B, DATA_C,
DATA_N
Input High Voltage, VINH
2.4
V
VDD = 3.3 V ± 10%
Input Current, IIN
2
40
nA
Input = VDD = 3.3 V
Input Low Voltage, VINL
0.8
V
VDD = 3.3 V ± 10%
Input Current, IIN
5
180
nA
Input = 0 V, VDD = 3.3 V
Input Capacitance, CIN
10
pF
LOGIC INPUT—RESET
Input High Voltage, VINH
2.4
V
VDD = 3.3 V ± 10%
Input Current, IIN
80
160
nA
Input = VDD = 3.3 V
Input Low Voltage, VINL
0.8
V
VDD = 3.3 V ± 10%
Input Current, IIN
−8
+11
µA
Input = 0 V, VDD = 3.3 V
Input Capacitance, CIN
10
pF
LOGIC OUTPUTS—IRQ0, IRQ1, MISO/HSD,
CLKOUT, SYNC, VT_A, VT_B, VT_C, VT_N,
ZX/DREADY, RESET_EN
VDD = 3.3 V ± 10%
Output High Voltage, VOH
2.4
V
VDD = 3.3 V
ISOURCE
4.8
mA
Output Low Voltage, VOL
0.4
V
VDD = 3.3 V ± 10%
ISINK
4.8
mA
CF1, CF2, CF3/HSCLK
Output High Voltage, VOH
2.4
V
VDD = 3.3 V ± 10%
ISOURCE
8
mA
Output Low Voltage, VOL
0.4
V
VDD = 3.3 V ± 10%
ISINK
8.5
mA
POWER SUPPLY
For specified performance
VDD Pin
2.97
3.63
V
Minimum = 3.3 V − 10%; maximum = 3.3 V
+ 10%
IDD
10.6
15.5
mA
1
See the Typical Performance Characteristics section.
2
See the Terminology section for a definition of the parameters.
3
XTALIN/XTALOUT total capacitances refer to the net capacitances on each pin. Each capacitance is the sum of the parasitic capacitance at the pin and the capacitance
of the ceramic capacitor connected between the pin and GND. See the ADE7978 and ADE7933/ADE7932 Clocks section for more information.


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