전자부품 데이터시트 검색엔진
  Korean  ▼
ALLDATASHEET.CO.KR

X  

AD7712AR-REEL 데이터시트(PDF) 7 Page - Analog Devices

부품명 AD7712AR-REEL
상세설명  LC2MOS Signal Conditioning ADC
Download  28 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
제조업체  AD [Analog Devices]
홈페이지  http://www.analog.com
Logo AD - Analog Devices

AD7712AR-REEL 데이터시트(HTML) 7 Page - Analog Devices

Back Button AD7712AR-REEL Datasheet HTML 3Page - Analog Devices AD7712AR-REEL Datasheet HTML 4Page - Analog Devices AD7712AR-REEL Datasheet HTML 5Page - Analog Devices AD7712AR-REEL Datasheet HTML 6Page - Analog Devices AD7712AR-REEL Datasheet HTML 7Page - Analog Devices AD7712AR-REEL Datasheet HTML 8Page - Analog Devices AD7712AR-REEL Datasheet HTML 9Page - Analog Devices AD7712AR-REEL Datasheet HTML 10Page - Analog Devices AD7712AR-REEL Datasheet HTML 11Page - Analog Devices Next Button
Zoom Inzoom in Zoom Outzoom out
 7 / 28 page
background image
REV. F
AD7712
–7–
PIN FUNCTION DESCRIPTION
Pin Mnemonic
Function
1
SCLK
Serial Clock. Logic input/output, depending on the status of the MODE pin. When MODE is high, the
device is in its self-clocking mode, and the SCLK pin provides a serial clock output. This SCLK becomes
active when
RFS or TFS goes low, and it goes high impedance when either RFS or TFS returns high or when
the device has completed transmission of an output word. When MODE is low, the device is in its external
clocking mode, and the SCLK pin acts as an input. This input serial clock can be a continuous clock with all
data transmitted in a continuous train of pulses. Alternatively, it can be a noncontinuous clock with the
information being transmitted to the AD7712 in smaller batches of data.
2
MCLK IN
Master Clock Signal for the Device. This can be provided in the form of a crystal or external clock. A crystal can
be tied across the MCLK IN and MCLK OUT pins. Alternatively, the MCLK IN pin can be driven with a
CMOS-compatible clock and MCLK OUT left unconnected. The clock input frequency is nominally 10 MHz.
3
MCLK OUT
When the master clock for the device is a crystal, the crystal is connected between MCLK IN and MCLK OUT.
4A0Address Input. With this input low, reading and writing to the device is to the control register. With this input
high, access is to either the data register or the calibration registers.
5
SYNC
Logic Input. Allows for synchronization of the digital filters when using a number of AD7712s. It resets
the nodes of the digital filter.
6
MODE
Logic Input. When this pin is high, the device is in its self-clocking mode. With this pin low, the device is in its
external clocking mode.
7
AIN1(+)
Analog Input Channel 1. Positive input of the programmable gain differential analog input. The AIN1(+) input
is connected to an output current source that can be used to check that an external transducer has burned out
or gone open circuit. This output current source can be turned on/off via the control register.
8
AIN1(–)
Analog Input Channel 1. Negative input of the programmable gain differential analog input.
9
STANDBY
Logic Input. Taking this pin low shuts down the internal analog and digital circuitry, reducing power
consumption to less than 50
µW.
10
TP
Test Pin. Used when testing the device. Do not connect anything to this pin.
11
VSS
Analog Negative Supply, 0 V to –5 V. Tied to AGND for single-supply operation. The input voltage on AIN1
should not go > 30 mV negative w.r.t. VSS for correct operation of the device.
12
AVDD
Analog Positive Supply Voltage, 5 V to 10 V.
13
VBIAS
Input Bias Voltage. This input voltage should be set such that VBIAS + 0.85
VREF < AVDD and VBIAS – 0.85
VREF > VSS where VREF is REF IN(+) – REF IN(–). Ideally, this should be tied halfway between AVDD
and VSS. Thus, with AVDD = +5 V and VSS = 0 V, it can be tied to REF OUT; with AVDD = +5 V and VSS =
–5 V, it can be tied to AGND, while with AVDD = +10 V, it can be tied to +5 V.
14
REF IN(–)
Reference Input. The REF IN(–) can lie anywhere between AVDD and VSS provided REF IN(+) is greater
than REF IN(–).
15
REF IN(+)
Reference Input. The reference input is differential providing that REF IN(+) is greater than REF IN(–).
REF IN(+) can lie anywhere between AVDD and VSS.
16
REF OUT
Reference Output. The internal 2.5 V reference is provided at this pin. This is a single-ended output
that is referred to AGND.
17
AIN2
Analog Input Channel 2. High level analog input that accepts an analog input voltage range of
±4
VREF/GAIN. At the nominal VREF of +2.5 V and a gain of 1, the AIN2 input voltage range is
±10 V.
18
AGND
Ground Reference Point for Analog Circuitry.
19
TFS
Transmit Frame Synchronization. Active low logic input used to write serial data to the device with serial
data expected after the falling edge of this pulse. In the self-clocking mode, the serial clock becomes active
after
TFS goes low. In the external clocking mode, TFS must go low before the first bit of the data-word
is written to the part.
20
RFS
Receive Frame Synchronization. Active low logic input used to access serial data from the device. In the
self-clocking mode, both the SCLK and SDATA lines become active after
RFS goes low. In the external
clocking mode, the SDATA line becomes active after
RFS goes low.


유사한 부품 번호 - AD7712AR-REEL

제조업체부품명데이터시트상세설명
logo
Analog Devices
AD7712AR-REEL AD-AD7712AR-REEL Datasheet
258Kb / 28P
   LC2MOS Signal Conditioning ADC
REV. F
AD7712AR-REEL AD-AD7712AR-REEL Datasheet
304Kb / 29P
   Signal Conditioning ADC
AD7712AR-REEL7 AD-AD7712AR-REEL7 Datasheet
258Kb / 28P
   LC2MOS Signal Conditioning ADC
REV. F
AD7712AR-REEL7 AD-AD7712AR-REEL7 Datasheet
304Kb / 29P
   Signal Conditioning ADC
More results

유사한 설명 - AD7712AR-REEL

제조업체부품명데이터시트상세설명
logo
Analog Devices
AD7712 AD-AD7712 Datasheet
229Kb / 28P
   LC2MOS Signal Conditioning ADC
REV. E
AD7712 AD-AD7712_04 Datasheet
258Kb / 28P
   LC2MOS Signal Conditioning ADC
REV. F
AD7712ANZ AD-AD7712ANZ Datasheet
258Kb / 28P
   LC2MOS Signal Conditioning ADC
REV. F
AD7712ARZ AD-AD7712ARZ Datasheet
258Kb / 28P
   LC2MOS Signal Conditioning ADC
REV. F
AD7713ARZ AD-AD7713ARZ Datasheet
271Kb / 28P
   LC2MOS Loop-Powered Signal Conditioning ADC
REV. D
AD7713ARZ AD-AD7713ARZ Datasheet
271Kb / 28P
   LC2MOS Loop-Powered Signal Conditioning ADC
REV. D
AD7713 AD-AD7713 Datasheet
516Kb / 28P
   LC2MOS Loop-Powered Signal Conditioning ADC
REV. C
AD7711ANZ AD-AD7711ANZ Datasheet
301Kb / 28P
   LC2MOS Signal Conditioning ADC with RTD Excitation Currents
REV. G
AD7711A AD-AD7711A Datasheet
222Kb / 27P
   LC2MOS Signal Conditioning ADC with RTD Current Source
REV. C
AD7711ARZ AD-AD7711ARZ Datasheet
301Kb / 28P
   LC2MOS Signal Conditioning ADC with RTD Excitation Currents
REV. G
More results


Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28


데이터시트 다운로드

Go To PDF Page


링크 URL




개인정보취급방침
ALLDATASHEET.CO.KR
ALLDATASHEET 가 귀하에 도움이 되셨나요?  [ DONATE ] 

Alldatasheet는?   |   광고문의   |   운영자에게 연락하기   |   개인정보취급방침   |   링크교환   |   제조사별 검색
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com