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AM28F512 ๋ฐ์ดํ„ฐ์‹œํŠธ(HTML) 2 Page - Advanced Micro Devices

๋ถ€ํ’ˆ๋ช… AM28F512
์ƒ์„ธ๋‚ด์šฉ  512 Kilobit (64 K x 8-Bit) CMOS 12.0 Volt, Bulk Erase Flash Memory
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์ œ์กฐ์‚ฌ  AMD [Advanced Micro Devices]
ํ™ˆํŽ˜์ด์ง€  http://www.amd.com
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AM28F512 ๋ฐ์ดํ„ฐ์‹œํŠธ(HTML) 2 Page - Advanced Micro Devices

 
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Am28F512
write cycles, the command register internally latches
address and data needed for the programming and
erase operations. For system design simplification, the
Am28F512 is designed to support either WE# or CE#
controlled writes. During a system write cycle, ad-
dresses are latched on the falling edge of WE# or CE#
whichever occurs last. Data is latched on the rising edge
of WE# or CE# whichever occurs first. To simplify the fol-
lowing discussion, the WE# pin is used as the write cycle
control pin throughout the rest of this text. All setup and
hold times are with respect to the WE# signal.
AMDโ€™s Flash technology combines years of EPROM
and EEPROM experience to produce the highest levels
of quality, reliability, and cost effectiveness. The
Am28F512 electrically erases all bits simultaneously
using Fowler-Nordheim tunneling. The bytes are pro-
gra mme d one byte at a time using the EPRO M
programming mechanism of hot electron injection.
BLOCK DIAGRAM
PRODUCT SELECTOR GUIDE
Family Part Number
Am28F512
Speed Options (VCC = 5.0 V ยฑ 10%)
-70
-90
-120
-150
-200
Max Access Time (ns)
70
90
120
150
200
CE# (E#) Access (ns)
70
90
120
150
200
OE# (G#) Access (ns)
35
35
50
55
55
Erase
Voltage
Switch
State
Control
Command
Register
Program
Voltage
Switch
Chip Enable
Output Enable
Logic
Y-Decoder
X-Decoder
Y-Gating
524,288
Bit
Cell Matrix
11561G-1
A0โ€“A15
OE#
CE#
WE#
VSS
VCC
To Array
DQ0โ€“DQ7
Input/Output
Buffers
Data
Latch
VPP
Address
Latch
Low VCC
Detector
Program/Erase
Pulse Timer


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