전자부품 데이터시트 검색엔진
  Korean  ▼

Delete All
ON OFF
ALLDATASHEET.CO.KR

X  

Preview PDF Download HTML

AM29BDS323D 데이터시트(HTML) 2 Page - Advanced Micro Devices

부품명 AM29BDS323D
상세내용  32 Megabit (2 M x 16-Bit) CMOS 1.8 Volt-only Simultaneous Read/Write, Burst Mode Flash Memory
Download  44 Pages
Scroll/Zoom Zoom In 100% Zoom Out
제조사  AMD [Advanced Micro Devices]
홈페이지  http://www.amd.com
Logo AMD - Advanced Micro Devices

AM29BDS323D 데이터시트(HTML) 2 Page - Advanced Micro Devices

  AM29BDS323D 데이터시트 HTML 1Page - Advanced Micro Devices AM29BDS323D 데이터시트 HTML 2Page - Advanced Micro Devices AM29BDS323D 데이터시트 HTML 3Page - Advanced Micro Devices AM29BDS323D 데이터시트 HTML 4Page - Advanced Micro Devices AM29BDS323D 데이터시트 HTML 5Page - Advanced Micro Devices AM29BDS323D 데이터시트 HTML 6Page - Advanced Micro Devices AM29BDS323D 데이터시트 HTML 7Page - Advanced Micro Devices AM29BDS323D 데이터시트 HTML 8Page - Advanced Micro Devices AM29BDS323D 데이터시트 HTML 9Page - Advanced Micro Devices Next Button
Zoom Inzoom in Zoom Outzoom out
 2 / 44 page
background image
2
Am29BDS323D
P R E L I M INARY
GENERAL DESCRIPTION
The Am29BDS323 is a 32 Mbit, 1.8 Volt-only, simulta-
neous Read/Write, Burst Mode Flash memory device,
organized as 2,097,152 words of 16 bits each. This
device uses a single VCC of 1.7 to 1.9 V to read, pro-
gram, and erase the memory array. A 12.0-volt VPP
may be used for faster program performance if desired.
The device can also be programmed in standard
EPROM programmers.
The Am29BDS323 provides a burst access of 20 ns at
30 pF with initial access times of 120 ns at 30 pF. The
device operates within the industrial temperature range
of –40
°C to +85°C. The device is offered in the 47-ball
FBGA package.
Simultaneous Read/Write Operations with
Zero Latency
The Simultaneous Read/Write architecture provides
simultaneous operation by dividing the memory
space into two banks. The device can improve overall
system performance by allowing a host system to pro-
gram or erase in one bank, then immediately and si-
multaneously read from the other bank, with zero
latency. This releases the system from waiting for the
completion of program or erase operations.
The device is divided as shown in the following table:
The device uses Chip Enable (CE#), Write Enable
(WE#), Address Valid (AVD#) and Output Enable
(OE#) to control asynchronous read and write opera-
tions. For burst operations, the device additionally
requires Power Saving (PS), Ready (RDY), and Clock
(CLK). This implementation allows easy interface with
minimal glue logic to a wide range of microproces-
sors/microcontrollers for high performance read opera-
tions.
The device offers complete compatibility with the
JEDEC 42.4 single-power-supply Flash command
set standard. Commands are written to the command
register using standard microprocessor write timings.
Reading data out of the device is similar to reading
from other Flash or EPROM devices.
The host system can detect whether a program or
erase operation is complete by using the device sta-
tus bit DQ7 (Data# Polling) and DQ6/DQ2 (toggle
bits). After a program or erase cycle has been com-
pleted, the device automatically returns to reading
array data.
The sector erase architecture allows memory sec-
tors to be erased and reprogrammed without affecting
the data contents of other sectors. The device is fully
erased when shipped from the factory.
Hardware data protection measures include a low
VCC detector that automatically inhibits write opera-
tions during power transitions. The device also offers
three types of data protection at the sector level. The
sector lock/unlock command sequence disables or
re-enables both program and erase operations in any
sector. When at VIL, WP# locks the two outermost sec-
tors. Finally, when VPP is at VIL, all sectors are locked.
The device offers two power-saving features. When
addresses have been stable for a specified amount of
time, the device enters the automatic sleep mode.
The system can also place the device into the
standby mode. Power consumption is greatly re-
duced in both modes.
Bank A Sectors
Bank B Sectors
Quantity
Size
Quantity
Size
8
4 Kwords
48
32 Kwords
15
32 Kwords
8 Mbits total
24 Mbits total


Html Pages

1  2  3  4  5  6  7  8  9  10  11  12  13  14  15  16  17  18  19  20  21  22  23  24  25  26  27  28  29  30  31  32  33  34  35  36  37  38  39  40  41  42  43  44 


데이터시트 Download

Go To PDF Page


링크 URL



Privacy Policy
ALLDATASHEET.CO.KR
ALLDATASHEET 가 귀하에 도움이 되셨나요?  [ DONATE ]  

Alldatasheet는?   |   광고문의    |   운영자에게 연락하기   |   개인정보취급방침   |   즐겨찾기   |   링크교환   |   제조사별 검색
All Rights Reserved© Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn