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AM28F020A-150FC 데이터시트(PDF) 12 Page - Advanced Micro Devices |
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AM28F020A-150FC 데이터시트(HTML) 12 Page - Advanced Micro Devices |
12 / 35 page 12 Am28F020A FLASH MEMORY PROGRAM/ERASE OPERATIONS Embedded Erase Algorithm The automatic chip erase does not require the device to be entirely pre-programmed prior to executing the Embedded set-up erase command and Embedded erase command. Upon executing the Embedded erase command the device automatically will program and verify the entire memory for an all zero data pattern. The system is not required to provide any controls or timing during these operations. When the device is automatically verified to contain an all zero pattern, a self-timed chip erase and verify be- gin. The erase and verify operation are complete when the data on DQ7 is “1" (see Write Operation Status sec- tion) at which time the device returns to Read mode. The system is not required to provide any control or timing during these operations. When using the Embedded Erase algorithm, the erase automatically terminates when adequate erase margin has been achieved for the memory array (no erase ver- ify command is required). The margin voltages are in- ternally generated in the same manner as when the standard erase verify command is used. The Embedded Erase Set-Up command is a command only operation that stages the device for automatic electrical erasure of all bytes in the array. Embedded Erase Setup is performed by writing 30h to the com- mand register. To commence automatic chip erase, the command 30h must be written again to the command register. The au- tomatic erase begins on the rising edge of the WE and terminates when the data on DQ7 is “1" (see Write Op- eration Status section) at which time the device returns to Read mode. Figure 1 and Table 4 illustrate the Embedded Erase al- gorithm, a typical command string and bus operation. Table 4. Embedded Erase Algorithm Note: See AC and DC Characteristics for values of VPP parameters. The VPP power supply can be hard-wired to the device or switchable. When VPP is switched, VPPL may be ground, no connect with a resistor tied to ground, or less than VCC + 2.0 V. Refer to Functional Description. Bus Operations Command Comments Standby Wait for VPP Ramp to VPPH (see Note) Write Embedded Erase Setup Command Data = 30h Embedded Erase Command Data = 30h Read Data # Polling to Verify Erasure Standby Compare Output to FFh Read Available for Read Operations START Apply VPPH Erasure Completed Data# Poll from Device Write Embedded Erase Command Write Embedded Erase Setup Command 17502D-6 Figure 1. Embedded Erase Algorithm |
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