전자부품 데이터시트 검색엔진 |
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AM85C30 데이터시트(PDF) 7 Page - Advanced Micro Devices |
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AM85C30 데이터시트(HTML) 7 Page - Advanced Micro Devices |
7 / 194 page Table of Contents AMD 5.3.1 BRG Clock Source 5–8 . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.3.2 BRG Enabling/Disabling 5–8 . . . . . . . . . . . . . . . . . . . . . . 5.3.3 BRG Initialization 5–9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.4 Data Encoding/Decoding 5–9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.4.1 NRZ (Non-Return to Zero) 5–9 . . . . . . . . . . . . . . . . . . . . . 5.4.2 NRZI (Non-Return to Zero Inverted) 5–9 . . . . . . . . . . . . . 5.4.3 FM1 (Biphase Mark) 5–10 . . . . . . . . . . . . . . . . . . . . . . . . . 5.4.4 FM0 (Biphase Space) 5–10 . . . . . . . . . . . . . . . . . . . . . . . . 5.4.5 Manchester Decoding 5–10 . . . . . . . . . . . . . . . . . . . . . . . . 5.4.6 Data Encoding Programming 5–10 . . . . . . . . . . . . . . . . . . . 5.5 Digital Phase-Locked Loop (DPLL) 5–10 . . . . . . . . . . . . . . . . . . . . 5.5.1 DPLL Clock Source 5–11 . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5.2 DPLL Enabling 5–11 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5.3 DPLL Modes 5–11 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5.3.1 NRZI Mode 5–11 . . . . . . . . . . . . . . . . . . . . . . . . . 5.5.3.2 FM Mode 5–12 . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5.3.3 Manchester Decoding Mode 5–13 . . . . . . . . . . . . 5.5.3.4 FM Mode DPLL Receive Status 5–13 . . . . . . . . . 5.5.4 DPLL Initialization 5–15 . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5.5 Am85C30-16 DPLL Operation at 32 MHz 5–15 . . . . . . . . . 5.5.5.1 Introduction 5–15 . . . . . . . . . . . . . . . . . . . . . . . . . 5.5.5.2 Benefit 5–15 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5.5.3 Applications 5–15 . . . . . . . . . . . . . . . . . . . . . . . . . 5.5.5.4 Description 5–15 . . . . . . . . . . . . . . . . . . . . . . . . . 5.5.5.5 Competition 5–15 . . . . . . . . . . . . . . . . . . . . . . . . . 5.6 Diagnostic Modes 5–15 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.6.1 Local Loopback 5–16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.6.2 Auto Echo 5–16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Chapter 6 Register Description 6.1 Introduction 6–3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.2 Write Registers 6–5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.2.1 Write Register 0 (Command Register) 6–5 . . . . . . . . . . . . 6.2.2 Write Register 1 (Transmit/Receive Interrupt and Data Transfer Mode Definition) 6–7 . . . . . . . . . . . . . . 6.2.3 Write Register 2 (Interrupt Vector) 6–9 . . . . . . . . . . . . . . . 6.2.4 Write Register 3 (Receive Parameters and Control) 6–10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.2.5 Write Register 4 (Transmit/Receiver Miscellaneous Parameters and Modes) 6–11 . . . . . . . . . . 6.2.6 Write Register 5 (Transmit Parameter and Controls) 6–13 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.2.7 Write Register 6 (SYNC Characters or SDLC Address Field) 6–15 . . . . . . . . . . . . . . . . . . . . . . . . . 6.2.8 Write Register 7 (SYNC Character or SDLC FLAG/SDLC Option Register) 6–17 . . . . . . . . . . . . . . . . . . 6.2.9 Write Register 8 (Transmit Buffer) 6–18 . . . . . . . . . . . . . . . 6.2.10 Write Register 9 (Master Interrupt Control) 6–18 . . . . . . . . 6.2.11 Write Register 10 (Miscellaneous Transmitter/ Receiver Control Bits) 6–20 . . . . . . . . . . . . . . . . . . . . . . . . 6.2.12 Write Register 11 (Clock Mode Control) 6–23 . . . . . . . . . . 6.2.13 Write Register 12 (Lower Byte of Baud Rate Generator Time Constant) 6–26 . . . . . . . . . . . . . . . . 6.2.14 Write Register 13 (Upper Byte of Baud Rate Generator Time Constant) 6–26 . . . . . . . . . . . . . . . . 6.2.15 Write Register 14 (Miscellaneous Control Bits) 6–27 . . . . . 6.2.16 Write Register 15 (External/Status Interrupt Control) 6–29 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.3 Read Registers 6–30 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
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